ad1819a_initialization.bak

adsp21065例程代码 音频处理及其他 adsp2XXX源代码 在Vdsp++下应用

	/* sport1 receive frame sync divide register */
	R0 = 0x00FF0000;			/* SCKfrq(12.288M)/RFSfrq(48.0K)-1 = 0x00FF */
	dm(RDIV1) = R0;			

	/* sport1 transmit control register */
	R0 = 0x001C00F0;			/* 1 cyc mfd, data depend, slen = 15, sden & schen enabled */
	dm(STCTL1) = R0;			/* sport 0 transmit control register */

	/* sport1 receive and transmit multichannel word enable registers */
	R0 = 0x0000001F;  			/* enable receive channels 0-4 */	
	dm(MRCS1) = R0;	
	R0 = 0x0000007F;  			/* enable transmit channels 0-6 */
	dm(MTCS1) = R0;			

	/* sport1 transmit and receive multichannel companding enable registers */
	R0 = 0x00000000;			/* no companding */
	dm(MRCCS1) = R0;			/* no companding on receive */
	dm(MTCCS1) = R0;			/* no companding on transmit */

	RTS;

/*----------------------------------------------------------------------------------*/
/* 			               DMA Controller Programming For SPORT1                    */
/*----------------------------------------------------------------------------------*/

Program_DMA_Controller:	
	r1 = 0x0001FFFF;				/* cpx register mask */

	/* sport1 dma control tx chain pointer register */
	r0 = tx_buf;
	dm(xmit_tcb + 7) = r0;          /* internal dma address used for chaining*/
	r0 = 1;
	dm(xmit_tcb + 6) = r0;          /* DMA internal memory DMA modifier */
	r0 = 7;
	dm(xmit_tcb + 5) = r0;          /* DMA internal memory buffer count */
	r0 = xmit_tcb + 7;				/* get DMA chaining internal mem pointer containing tx_buf address */
	r0 = r1 AND r0;					/* mask the pointer */
	r0 = BSET r0 BY 17;				/* set the pci bit */
	dm(xmit_tcb + 4) = r0;          /* write DMA transmit block chain pointer to TCB buffer */
	dm(CPT1A) = r0;                 /* transmit block chain pointer, initiate tx0 DMA transfers */

	/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
	/* - Note: Tshift0 & TX0 will be automatically loaded with the first 2 values in the   - */
	/* - Tx buffer. The Tx buffer pointer ( II3 ) will increment by 2x the modify value    - */
	/* - ( IM3 ).                                                			       	       - */
	/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
	
	/* sport1 dma control rx chain pointer register */
	r0 = rx_buf;
	dm(rcv_tcb + 7) = r0;           /* internal dma address used for chaining */
	r0 = 1;
	dm(rcv_tcb + 6) = r0;           /* DMA internal memory DMA modifier */
	r0 = 5;
	dm(rcv_tcb + 5) = r0;           /* DMA internal memory buffer count */
	r0 = rcv_tcb + 7;
	r0 = r1 AND r0;					/* mask the pointer */
	r0 = BSET r0 BY 17;				/* set the pci bit */
	dm(rcv_tcb + 4) = r0;           /* write DMA receive block chain pointer to TCB buffer*/
	dm(CPR1A) = r0;                 /* receive block chain pointer, initiate rx0 DMA transfers */
	
	RTS;

/* -------------------------------------------------------------------------------------- */
/*                               AD1819A Codec Initialization                             */
/* -------------------------------------------------------------------------------------- */

AD1819_Codec_Initialization:
	bit set imask SPT1I;    		/* enable sport0 x-mit interrupt */

Wait_Codec_Ready:					/* Wait for CODEC Ready State */
	R0 = DM(rx_buf + 0);			/* get bit 15 status bit from AD1819 tag phase slot 0 */
	R1 = 0x8000;					/* mask out codec ready bit in tag phase */
	R0 = R0 AND R1;					/* test the codec ready status flag bit */
	IF EQ JUMP Wait_Codec_Ready;	/* if flag is lo, continue to wait for a hi */
	
	idle;							/* wait for a couple of TDM audio frames to pass */
	idle;			

Initialize_1819_Registers:
	i4 = Init_Codec_Registers;      /* pointer to codec initialization commands */
	r15 = ENABLE_VFbit_SLOT1_SLOT2;	/* enable valid frame bit, and slots 1 and 2 valid data bits */

	LCNTR = 17, DO Codec_Init UNTIL LCE;
		dm(tx_buf + TAG_PHASE) = r15;			/* set valid slot bits in tag phase for slots 0, 1 , 2 */
		r1 = dm(i4, 1);                			/* fetch next codec register address */
		dm(tx_buf + COMMAND_ADDRESS_SLOT) = r1;	/* put fetched codec register address into tx slot 1 */
		r1 = dm(i4, 1);							/* fetch register data contents */
		dm(tx_buf + COMMAND_DATA_SLOT) = r1;	/* put fetched codec register data into tx slot 2 */
Codec_Init:	idle;								/* wait until TDM frame is transmitted */
	
/*------------------------------------------------------------------------------------------------------*/
/* Verify integrity of AD1819a indexed control register states to see if communication was successful 	*/
/*------------------------------------------------------------------------------------------------------*/
/* This section of codes is for debugging/verification of AD1819 registers.  Theses instructions      	*/
/* initiate codec read requests of registers shown in the Init_Codec_Registers buffer.  The results   	*/
/* of the read requests are placed in an output buffer called Codec_Init_Results, in which even       	*/
/* DSP memory addresses contain the AD1819A register address, and the DSP's odd address in the buffer  	*/
/* contains the register data for the AD1819A address.  The AD1819A registers can then be verified with */
/* a JTAG emulator or debug monitor program.  This section of code can be removed after debug.	      	*/
/*------------------------------------------------------------------------------------------------------*/

verify_reg_writes:
	i4 = Init_Codec_Registers;
	m4 = 2;
	i5 = Codec_Init_Results;
	r15 = ENABLE_VFbit_SLOT1;				/* enable valid frame bit, and slots 1 data bits */

	LCNTR = 17, Do ad1819_register_status UNTIL LCE;
		dm(tx_buf + TAG_PHASE) = r15;		/* set valid slot bits in tag phase for slots 0, 1 , 2 */
		r1 = dm(i4,2);						/* get indexed register address that is to be inspected */
		r2 = 0x8000;						/* set bit #15 for read request in command address word */
		r1 = r1 OR r2;						/* OR read request with the indirect register value */
		dm(tx_buf + COMMAND_ADDRESS_SLOT) = r1;	/* send value out of command address timeslot */
		idle;								/* wait for 2 audio frame to go by, latency in getting data */
		idle;
		r3 = dm(rx_buf + STATUS_ADDRESS_SLOT);
		dm(i5,1) = r3;
		r3 = dm(rx_buf + STATUS_DATA_SLOT);	/* fetch value of requested indexed register data */
		dm(i5,1) = r3;						/* store to results buffer */
ad1819_register_status: nop;

	/* For variable sample rate support, you must powerdown and powerback up the ADCs and DACs
	so that the incoming ADC data and DAC requests occur in left/right pairs */
PowerDown_DACs_ADCs:
	idle;
	r15 = ENABLE_VFbit_SLOT1_SLOT2;			/* enable valid frame bit, and slots 1 and 2 valid data bits */
	dm(tx_buf + TAG_PHASE) = r15;			/* set valid slot bits in tag phase for slots 0, 1 , 2 */
	r0=POWERDOWN_CTRL_STAT;				
	dm(tx_buf + COMMAND_ADDRESS_SLOT) = r0;
	r0=0x0300;								/* power down all DACs/ADCs */
	dm(tx_buf + COMMAND_DATA_SLOT) = r0;
	idle;
	idle;

	LCNTR = AD1819_RESET_CYCLES-2, DO reset_loop UNTIL LCE;
reset_loop:	NOP;							/* wait for the min RESETb lo spec time */

	idle;
	r15 = ENABLE_VFbit_SLOT1_SLOT2;			/* enable valid frame bit, and slots 1 and 2 valid data bits */
	dm(tx_buf + TAG_PHASE) = r15;			/* set valid slot bits in tag phase for slots 0, 1 , 2 */
	r0=POWERDOWN_CTRL_STAT;					/* address to write to  */
	dm(tx_buf + COMMAND_ADDRESS_SLOT) = r0;
	r0=0;									/* power up all DACs/ADCs */
	dm(tx_buf + COMMAND_DATA_SLOT) = r0;
	idle;
	idle;

	LCNTR = AD1819_WARMUP_CYCLES-2, DO warmup_loop2 UNTIL LCE;
warmup_loop2: NOP;                  		/* wait for AD1819 warm-up */    


/* ---------------------------------------------------------------------------------------------------- */

	bit clr imask SPT1I;     				/* disable sport1 xmit  */

Install_ISR_SPORT1_Tx_ISR:      
	/* Use SPORT1 TX interrupt service function call for audio processing */			
        /* install the transmit interrupt function call to replace the initial RTI instruction */
	/* "JUMP Process_AD1819_Audio_Samples" instruction into PX (0x063E 0000 xxxx). */
	/* xxxx = address of Process_AD1819_Audio_Samples */
	PX2 = 0x063e0000;					/* Upper 32 bit Opcode for 'JUMP xxxx' instruction */
	PX1 = Process_AD1819_Audio_Samples;	/* Lower 16 bits of Opcode contain jump address */
	PM(spt1_svc) = PX;					/* copy to 0x34 - SPORT1 interrupt vect location */
       		
	RTS; 								/* End of AD1819A Initialization */

/* ------------------------------------------------------------------------------------------- */
 .endseg;