📄 geq_c6711_dsk.mdl
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System {
Name "geq_C6711_dsk"
Location [299, 119, 973, 420]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "ADC"
Ports [0, 1]
Position [15, 83, 105, 127]
FontSize 10
SourceBlock "c6711dsklib/ADC"
SourceType "C6711DSK ADC"
ADCsource "Line In"
MicGain off
OutputDataType "Double"
Scaling "Normalize"
SourceGain "0.0"
FrameSize "64"
}
Block {
BlockType Reference
Name "DAC"
Ports [1]
Position [520, 123, 610, 167]
FontSize 10
SourceBlock "c6711dsklib/DAC"
SourceType "C6711DSK DAC"
Scaling "Normalize"
DacAtten "0.0"
OverflowMode "Saturate"
}
Block {
BlockType Reference
Name "Digital\nFilter Design"
Ports [1, 1]
Position [220, 32, 285, 88]
UserDataPersistent on
UserData "DataTag0"
FontSize 10
SourceBlock "dsparch4/Digital\nFilter Design"
SourceType "Digital Filter Design"
}
Block {
BlockType Reference
Name "Digital\nFilter Design1"
Ports [1, 1]
Position [225, 122, 290, 178]
UserDataPersistent on
UserData "DataTag1"
FontSize 10
SourceBlock "dsparch4/Digital\nFilter Design"
SourceType "Digital Filter Design"
}
Block {
BlockType Reference
Name "Digital\nFilter Design2"
Ports [1, 1]
Position [225, 227, 290, 283]
UserDataPersistent on
UserData "DataTag2"
FontSize 10
SourceBlock "dsparch4/Digital\nFilter Design"
SourceType "Digital Filter Design"
}
Block {
BlockType Gain
Name "Gain"
Position [340, 45, 370, 75]
}
Block {
BlockType Gain
Name "Gain1"
Position [345, 135, 375, 165]
}
Block {
BlockType Gain
Name "Gain2"
Position [350, 240, 380, 270]
}
Block {
BlockType Sum
Name "Sum"
Ports [3, 1]
Position [440, 108, 465, 177]
ShowName off
Inputs "|+++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Line {
SrcBlock "Digital\nFilter Design"
SrcPort 1
DstBlock "Gain"
DstPort 1
}
Line {
SrcBlock "Digital\nFilter Design2"
SrcPort 1
DstBlock "Gain2"
DstPort 1
}
Line {
SrcBlock "Digital\nFilter Design1"
SrcPort 1
DstBlock "Gain1"
DstPort 1
}
Line {
SrcBlock "Gain2"
SrcPort 1
Points [20, 0; 0, -90]
DstBlock "Sum"
DstPort 3
}
Line {
SrcBlock "Gain1"
SrcPort 1
DstBlock "Sum"
DstPort 2
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [25, 0; 0, 75]
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "DAC"
DstPort 1
}
Line {
SrcBlock "ADC"
SrcPort 1
Points [35, 0; 0, 50]
Branch {
Points [0, -5]
DstBlock "Digital\nFilter Design1"
DstPort 1
}
Branch {
Points [0, 100]
DstBlock "Digital\nFilter Design2"
DstPort 1
}
Branch {
Points [0, -95]
DstBlock "Digital\nFilter Design"
DstPort 1
}
}
}
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