syslib.c

大名鼎鼎的mpc8260的bsp源代码

/* sysLib.c - Motorola 860ads board system-dependent library */

/* Copyright 1984-1997 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01m,18mar99,cn   added support for motCpmEnd driver (SPR# 25839).
01l,03dec98,mas  added GUARDED attributes to non-local memory areas mapped in
		 sysPhysMemDesc[]. (SPR 23674)
01k,12nov98,cn   changed sysFecEnetEnable(), sysFecEnetDisable() to
                 enable/disable the PHY device.
01j,09nov98,cn   added support for FADS860T boards and FEC.
01i,08may98,gls  added clear of all cpm interrups in sysToMonitor
01h,08mar98,gls	 added checks to allow BSP to work with the PPC850FADS
01g,18feb98,gls  added code to allow the BSP to  work with the PPC823FADS
01f,12nov97,map  updated to use ppc860Timer.c [SPR# 9366]
01e,21feb97,mas  removed NOMANUAL, made sysHwInit2() visible to 'man' (SPR 7879)
01d,11nov96,tam  added power management mode initialization.
01c,06nov96,tpr  reworked sysHwInit().
01b,28may96,dzb  added Ethernet driver support routines.
		 added port initialization, and increased system to 24Mhz.
01a,19apr96,tpr  written.
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    ppc860Timer.c	- PowerPC/860 Timer library
    sysMotCpmEnd.c	- configuration module for the motCpmEnd driver

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "logLib.h"
#include "stdio.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "drv/pci/pciConfigLib.h"
#include "arch/ppc/vxPpcLib.h"
#include "private/vmLibP.h"

#include "drv/multi/ppc860Siu.h"
#include "ads860.h"

#ifdef	INCLUDE_CPM
#include "drv/netif/if_cpm.h"
#endif


#include "esf.h"
#include "excLib.h"

#include "flashLib.h"

IMPORT int	sysPciErr();


#define PCI_HOST_BUS_NBR        0       /* number of bus on far side of  */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    LOCAL_MEM_SIZE ,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
    },

    {
    (void *) FLASH_START,
    (void *) FLASH_START,
    (FLASH_SIZE_1 + FLASH_SIZE_2),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT /*changed 30aug03,lyx*/
    },
    
    {
    (void *) SRAM_MEM_ADRS,
    (void *) SRAM_MEM_ADRS,
    SRAM_MEM_SIZE ,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },


	/*FPGA_CS added by zhao 030904*/
    
	{
    (void *) FPGA_MEM_ADRS,
    (void *) FPGA_MEM_ADRS,
    FPGA_MEM_SIZE ,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    {
    (void *) INTERNAL_MEM_MAP_ADDR,
    (void *) INTERNAL_MEM_MAP_ADDR,
    INTERNAL_MEM_MAP_SIZE,		/* 64 k - Internal Memory Map */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    /* PCI Host bridge, on local bus */
    {
    (void *) CPU_PCI_BRIDGE_BA,
    (void *) CPU_PCI_BRIDGE_BA,
    CPU_PCI_BRIDGE_SIZE,		/* 64 k - Internal Memory Map */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

 /* PCI Host bridge-ct69000 on local bus */
    {
    (void *) CPU_PCI_CT69000_BA,
    (void *) CPU_PCI_CT69000_BA,
    CPU_PCI_CT69000_SIZE,		/* 64 k - Internal Memory Map */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) ROM_BASE_ADRS,
    (void *) ROM_BASE_ADRS,
    ROM_SIZE,				/* Flach memory */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int   sysBus      = BUS;                /* system bus type (VME_BUS, etc) */
int   sysCpu      = CPU;                /* system CPU type (PPC860) */
char *sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
char *sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int   sysProcNum;			/* processor number of this CPU */
int   sysFlags;				/* boot flags */
char  sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char  sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
BOOL  sysVmeEnable = FALSE;		/* by default no VME */

#ifdef	INCLUDE_CPM
/* XXX set the following array to a unique Ethernet hardware address XXX */

/* last 5 nibbles are board specific, initialized in sysHwInit */

unsigned char sysCpmEnetAddr [6] = {0x08, 0x00, 0x3e, 0x03, 0x22, 0x35};

extern STATUS cpmattach();

#endif	/* INCLUDE_CPM */

/* locals */

void sysCpmEnetDisable (int unit);
void sysCpmEnetIntDisable (int unit);

#ifdef INCLUDE_MOT_FEC

/* set the following array to a unique Ethernet hardware address */

unsigned char sysFecEnetAddr [6] = {0x08, 0x00, 0x3e, 0x03, 0x22, 0x22};


IMPORT STATUS sysFecEnetDisable (UINT32 motCpmaddr);

#endif /* INCLUDE_MOT_FEC */

#include "pci/pciConfigLib.c"
#include "pci/pciConfigShow.c"  /*added for pci device 18aug03,lyx*/
#include "sysSerial.c"
#include "intrCtl/ppc860Intr.c"
#include "mem/nullNvRam.c"
#include "timer/ppc860Timer.c"		/* PPC860 & 821 have on chip timers */
#ifdef INCLUDE_CPM
#   include "sysMotCpmEnd.c"		/* configuration module for motCpmEnd */
#endif	/* INCLUDE_CPM */


#include "i2cMcp.c"

#include "I2c_app.c"           /*yang*/          /* I2C bus access */
#include "Scp.c" 
#include "u.c"
#include "codec.c"
#include "fpga.c"
#include "PCIConfig.c"


#include "SelfCheck.c" 

#include "Random.c"

/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/

char * sysModel (void)
    {
    return ("Motorola ADS - PowerPC 860");
    }

/******************************************************************************
*
* sysBspRev - return the bsp version with the revision eg 1.0/<x>
*
* This function returns a pointer to a bsp version with the revision.
* for eg. 1.0/<x>. BSP_REV defined in config.h is concatanated to
* BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }
/******************************************************************************
*
* reset and light - reset 4 chips, include U33, U34, 145572
*
* RETURNS: NULL
*/
void reset_chips(void)
{
   int immrVal = INTERNAL_MEM_MAP_ADDR;
/*   zao orig
   *PDPAR(immrVal) &= ~0x00F0;
   *PDDIR(immrVal)  |= 0x00F0;   
   *PDDAT(immrVal) &= ~0x00F0; 
    taskDelay(sysClkRateGet ()/div);
   *PDDAT(immrVal) |= 0x00F0;     
   */

	int i=0;
   *PDPAR(immrVal) &= ~0x00F0;
   *PDDIR(immrVal)  |= 0x00F0;   
   *PDDAT(immrVal) &= ~0x00F0; /*pd8,pd9 <---0 for codec reset ;pd10,pd11 <---0 for U(Mc145572) reset*/
    for(i=0;i<2000;i++);
   *PDDAT(immrVal) |= 0x00F0;  /*pd8,pd9,pd10,pd11 <---1*/   

}

void SelfCheck(void)
{

	pCheckSelf=CheckSelfCreat(0);
	write(pCheckSelf->Smc1Id,"System Self Check Begin...\n",28);	
	CheckSelfProcess(pCheckSelf);
	dispalyHarrisLogo(pCheckSelf);
	CheckSelfDisplay(pCheckSelf);
      	printf ("HwId:%s\n", sysArkphyIDAddr);
	write(pCheckSelf->Smc1Id,"System Self Check End.\n",24);
	CheckSelfDistory(pCheckSelf);
		
	
}
/******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various feature of the MPC860ADS boards. It sets up
* the control registers, initializes various devices if they are present.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {
    int	immrVal = vxImmrGet();
    UINT32	qspanAdr;	/* QSpan device registers base address */

	*SIUMCR(immrVal) = 0x00610b00;
     /* set the SPLL to the value requested */

    * PLPRCR(immrVal) = (*PLPRCR(immrVal) & ~PLPRCR_MF_MSK) | 
				(SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT);

	/* PLPRCR = 0; SPLL_FREQ = 50M, CRISTAL = 50M */

    /* set the BRGCLK division factor */

    * SCCR(immrVal) = (* SCCR(immrVal) & ~SCCR_DFBRG_MSK) |
				(BRGCLK_DIV_FACTOR << SCCR_DFBRG_SHIFT);
    /* set the Periodic Timer A value */
     
    * MAMR(immrVal) = (* MAMR(immrVal) & ~MAMR_PTA_MSK) | 
				(PTA_VALUE << MAMR_PTA_SHIFT);	

    /* set the Periodic Timer PreScale */

    * MPTPR(immrVal) = PTP_VALUE;

    /* reset the port A */

    *PAPAR(immrVal) = 0x0000;
    *PADIR(immrVal) = 0x0000;
    *PAODR(immrVal) = 0x0000;

    /* reset the port B */

    *PBPAR(immrVal) = 0x0000000;
    *PBDIR(immrVal) = 0x0000000;
    *PBODR(immrVal) = 0x0000000;

    /* reset the port C */

    *PCPAR(immrVal) = 0x0000;
    *PCDIR(immrVal) = 0x0000;
    *PCSO(immrVal)  = 0x0000;

    /* reset the port D */

    *PDPAR(immrVal) = 0x0000;
    *PDDIR(immrVal) = 0x0000;


    *SICR(immrVal) = 0x0;		/* initialize SI/NMSI connections */

    /* Initialize interrupts */

    ppc860IntrInit(IV_LEVEL4); 	/* default vector level  yangdy*/





    /* make sure Ethernet is disabled */

    sysCpmEnetDisable (0);
    sysCpmEnetIntDisable (0);

#ifdef INCLUDE_MOT_FEC

    /* make sure the FEC is disabled */

    sysFecEnetDisable (immrVal);

#endif /* INCLUDE_MOT_FEC */

    /*
     * The power management mode is initialized here. Reduced power mode
     * is activated only when the kernel is iddle (cf vxPowerDown).
     * Power management mode is selected via vxPowerModeSet().
     * DEFAULT_POWER_MGT_MODE is defined in config.h.
     */

    vxPowerModeSet (DEFAULT_POWER_MGT_MODE);
    /*
     * Download I2C/SPI RISC microcode patch
     *
     * MUST RE-MAP THE I2C INTO IDMA1 at 0x1cc0 
     * with the following patch.
     */

   i2cMcp();


    /* initialization Qspan II  */
    qspanAdr = ((*BR5(immrVal)) & BR_BA_MSK);  /* Get Qspan Addr */

#if 0    
    SysQspanHwInit((PQSPAN)(qspanAdr));
    sysPCISpaceAssign();
#endif
    		/* 
		 * for QSPAN 1.2 and above we enable the MA_BE_D bit in
		 * the MISC_CTL register, which provides normal 
		 * termination to the Processor Bus, and therefore we	
		 * can use the generic PCI read/write calls.
		 */