fpga.h

大名鼎鼎的mpc8260的bsp源代码

#ifndef __FPGA_H_

    #define __FPGA_H_

/*--------------FPGA chip control register address -------------------*/
	#if 0
    #define FR_FTAHH  0x50000000 /*first tone address high 31~24 bit in FPGA block memory*/
    #define FR_FTAHL  0x50000001/*first tone address high 23~16 bit in FPGA block memory*/
	#endif
    #define FR_FTALH  0x50000002/*first tone address low 11~8 bit in FPGA block memory*/
    #define FR_FTALL  0x50000003/*first tone address low 7~0 bit in FPGA block memory*/
	#if 0
    #define FR_FTTHH  0x50000004/*first tone timer1 high 31~24 bit in FPGA block memory*/
    #define FR_FTTHL  0x50000005/*first tone timer1 high 23~16 bit in FPGA block memory*/
	#endif
    #define FR_FTTLH  0x50000006/*first tone timer1 low 11~8 bit in FPGA block memory*/
    #define FR_FTTLL  0x50000007/*first tone timer1 low 7~0 bit in FPGA block memory*/
    #if 0
    #define FR_STAHH  0x50000008/*second tone address  high 31~24 bit in FPGA block memory*/
    #define FR_STAHL  0x50000009/*second tone address high 23~16 bit  in FPGA block memory*/
    #endif	
    #define FR_STALH  0x5000000A/*second tone address low 11~8 bit in FPGA block memory*/
    #define FR_STALL  0x5000000B/*second tone address low 7~0 bit in FPGA block memory*/
	#if 0
    #define FR_STTHH  0x5000000C/*second tone timer2 high 31~24 bit in FPGA block memory*/
    #define FR_STTHL  0x5000000D/*second tone timer2 high 23~16 bit in FPGA block memory*/
	#endif
    #define FR_STTLH  0x5000000E/*second tone timer2 low 11~8 bit in FPGA block memory*/
    #define FR_STTLL  0x5000000F/*second tone timer2 low 7~0 bit in FPGA block memory*/


	#define FR_PTC 0x50000020/*playing tone control register 1: start  0:stop*/


/*add 5.13 begin   --- 2 tone souce*/
	#if 0
    #define FR_FTAHH2  0x53000000 /*first tone address high 31~24 bit in FPGA block memory*/
    #define FR_FTAHL2  0x53000001/*first tone address high 23~16 bit in FPGA block memory*/
	#endif
    #define FR_FTALH2  0x53000002/*first tone address low 11~8 bit in FPGA block memory*/
    #define FR_FTALL2  0x53000003/*first tone address low 7~0 bit in FPGA block memory*/
	#if 0
    #define FR_FTTHH2  0x53000004/*first tone timer1 high 31~24 bit in FPGA block memory*/
    #define FR_FTTHL2  0x53000005/*first tone timer1 high 23~16 bit in FPGA block memory*/
	#endif
    #define FR_FTTLH2  0x53000006/*first tone timer1 low 11~8 bit in FPGA block memory*/
    #define FR_FTTLL2  0x53000007/*first tone timer1 low 7~0 bit in FPGA block memory*/
    #if 0
    #define FR_STAHH2  0x53000008/*second tone address  high 31~24 bit in FPGA block memory*/
    #define FR_STAHL2  0x53000009/*second tone address high 23~16 bit  in FPGA block memory*/
    #endif	
    #define FR_STALH2  0x5300000A/*second tone address low 11~8 bit in FPGA block memory*/
    #define FR_STALL2  0x5300000B/*second tone address low 7~0 bit in FPGA block memory*/
	#if 0
    #define FR_STTHH2  0x5300000C/*second tone timer2 high 31~24 bit in FPGA block memory*/
    #define FR_STTHL2  0x5300000D/*second tone timer2 high 23~16 bit in FPGA block memory*/
	#endif
    #define FR_STTLH2  0x5300000E/*second tone timer2 low 11~8 bit in FPGA block memory*/
    #define FR_STTLL2  0x5300000F/*second tone timer2 low 7~0 bit in FPGA block memory*/


	#define FR_PTC2 0x53000020/*playing tone control register 1: start  0:stop*/

/*add 5.13 end*/

	
	#if 0
	#define FR_B1U1 0x51000000/*B1 of  U1 register address*/
	#define FR_B2U1 0x51000004/*B2 of  U1 register address*/
	#define FR_B1U2 0x51000008/*B1 of  U2 register address*/
	#define FR_B2U2 0x5100000c/*B2 of  U2 register address*/

	#define FR_Codec1 0x51000010/*CODEC 1 register address*/
	#define FR_Codec2 0x51000014/*CODEC 2 register addres*/
	#endif
	#if 1
	#define FR_U1B1 0x51000000/*B1 of  U1 register address*/
	#define FR_U1B2 0x51000002/*B2 of  U1 register address*/
	#define FR_U2B1 0x51000004/*B1 of  U1 register address*/
	#define FR_U2B2 0x51000006/*B2 of  U1 register address*/


#if 0
	#define FR_Codec1_Channel1 0x51000010/*CODEC 1 channel1 register address*/
	#define FR_Codec1_Channel2 0x51000012/*CODEC 1 channel2 register addres*/
	#define FR_Codec2_Channel1 0x51000014/*CODEC 2 channel1 register address*/
	#define FR_Codec2_Channel2 0x51000016/*CODEC 2 channel2 register addres*/
#else
	#define FR_LEFT_HANDSET_REG  0x51000010/*left handset  register address*/
       #define FR_RIGHT_HANDSET_REG  0x51000012   /*right handset register addres*/
	#define FR_MICRO_SPEAKER_REG 0x51000014 /*micro and speaker register address*/ 
	#define FR_RECORD_REG 0x51000016
#endif
	#endif
	#define FR_Test 	  0x5100ffff/*test register*/
/*add 2004.3.2 */
	#define FR_U_Channel_Sel 0x55000020 /*to select u interface channel*/
	#define FR_RECORD_CONTROL      0x55000010/* control record */

	
	#define FNR_TX		0x54000000
	#define SNR_TX  		0x54000001
	#define FU_EN		0x54000002
	#define FNR_RX		0x54000004
	#define SNR_RX		0x54000005
	#define FBR_TX1		0x54000006
	#define FBR_TX2		0x54000007
	#define SBR_TX1		0x54000008
	#define SBR_TX2		0x54000009
	#define FBR_RX1		0x5400000a
	#define FBR_RX2		0x5400000b
	#define SBR_RX1		0x5400000c
	#define SBR_RX2		0x5400000d

	#define U_FREQREF   0x55000000
	

    typedef enum _Tone_Type_
    	{
    	SilentTone,
    	DialTone,
	    BusyTone,
    	RingBack,
    	PressingKey,
    	Confirmation,
    	StutteDial,
    	ErrorTone,
    	HoldTone,
    	QueuePrompt,
    	OffhookQueue,
    	InteralCampOn,
    	ExternalCampOn,
    	NoNotificationCampOn,
    	RingTone1,
    	RingTone2,
    	RingTone3,
    	RingTone4,
    	RingTone5,
    	RingTone6,
    	RingTone7,
    	RingTone8,
  	    RingTone9,
    	RingTone10,
    	DTMF1,
    	DTMF2,
    	DTMF3,
    	DTMF4,
    	DTMF5,
    	DTMF6,
    	DTMF7,
    	DTMF8,
    	DTMF9,
    	DTMF0,
    	DTFM_STAR,
    	DTFM_SHARP,
	MAX_TONE_TYPE
    	}sTone_type;

    #define ReadWord(address)		(*(unsigned short *)(address))
    #define ReadByte(address)		(*(unsigned char *)(address))
    #define WriteWord(address, w)	(*(unsigned short *)(address)=(w))
    #define WriteByte(address, b)	(*(unsigned char *)(address)=(b)) 

 /*------------ FPGA  interface------------------------------*/
    
int HW_Test_FPGA(unsigned char val);

#if 1
void HW_PlaySecondDialTone(unsigned char postion ,unsigned short tone_type,unsigned char PlayFlag,unsigned char U_channel);
void HW_Play_Tone(unsigned char postion ,unsigned short tone_type,unsigned char PlayFlag,unsigned char Codec_Sel,unsigned char Play_Second_tone);
/*void HW_Connect(unsigned char source_id,unsigned char destination_id);*/
#else
void HW_PlaySecondDialTone(unsigned short tone_type,unsigned char PlayFlag,unsigned char U_channel);
void HW_Play_Tone(unsigned short tone_type,unsigned char PlayFlag,unsigned char Codec_Sel,unsigned char Play_Second_tone);
void HW_Connect(unsigned char destination_id);
#endif

void HW_Disconnect(unsigned char dev);
void HW_Record_Begin(unsigned char Line);
void HW_Record_Stop(void);
void HW_LCDPower_Control(unsigned char val);
void HW_Record_Control(unsigned char val);
void playdial(unsigned char  postion,unsigned char channel_sel);
void playbusy(unsigned char  postion,unsigned char channel_sel);
void stop(unsigned char  postion,unsigned char channel_sel);









   #endif /* __FPGA_H_ */