pciconfig.c

来自「大名鼎鼎的mpc8260的bsp源代码」· C语言 代码 · 共 329 行

#include <vxworks.h>
#include <drv/pci/PCIConfigLib.h>
#include "PCIConfig.h"

UINT32 PCIDeviceTable[PCI_DEVICE_NUM] =
    {
    /* vendid+deviceid*/
    0x102c00c0
	};

UINT32	PCIDeviceBASE[PCI_DEVICE_NUM][2] =
{
	/*IO-space BASE,Memory-space BASE*/
	{0,0x80000000}

};

/******************************************************************************
*
* SysQspanHwInit - initialize the QSpan PCIBus bridge controller
*
* This function's purpose is to initialize the QSpan device.  This
* device spans the QBus to PCIBus.
*
* RETURNS: N/A
*/

void SysQspanHwInit(PQSPAN qspanAdr)
{
	/*Enable the qspan as the PCI Master*/
	qspanHostEnable(qspanAdr);

    /*
     * setup the synchronous bus grant and bus grant acknowledge,
     * setup the byte ordering: big endian or little endian
     * setup the master/slave mode
     * for QSPAN chips of rev. 1.2 or greater, set the Master Abort
     * bit to disable Bus error mapping
     */
     qspanAdr->misc_ctl = QSPAN_SET_S_BG | QSPAN_SET_S_BB |
		    QSPAN_BOC_BE | QSPAN_MA_BE_D | QSPAN_MSTSLV_3 ;	/*0x800*/

	/*setup the PCI BUS to Access the memory space*/
	qspanSpaceAccesses(qspanAdr,PCI_CS_MS);

	sysPCISpaceAssign();
	
	qspanIOControl(qspanAdr,PCI_CS_MS);
}



/******************************************************************************
*
* qspanHostReset - reset the QSpan PCIBus bridge controller
*
* This function's purpose is to reset the QSpan device.
*
* RETURNS: N/A
*/
void qspanHostReset
    (
    PQSPAN qspanAdr        /* base address of the QSpan device regs. */
    )
{

    /*
     * clear all PCI error status
     * disable SERR, and PERR
     * disable I/O-space, memory-space, and bus mastering
     */
	qspanAdr->pci_cs = QSPAN_CLR_D_PE | QSPAN_CLR_S_SERR | QSPAN_CLR_R_MA |
                QSPAN_CLR_R_TA | QSPAN_CLR_S_TA | QSPAN_CLR_DP_D;

    EIEIO_SYNC;
}

/******************************************************************************
*
* qspanHostEnable - enable the bridge
*
* This function enables I/O-space, memory-space, and bus mastering on
* the host.
*
* RETURNS: N/A
*/

void qspanHostEnable
    (
    PQSPAN      qspanAdr        /* base address of the QSpan device regs. */
    )
{
    UINT32 temp;

    /*
     * clear all QBus error status
     * enable QBus error log
     */

	qspanAdr->qb_errcs = QSPAN_ENABLE_ERR_LOG | QSPAN_CLR_QES;	/*0xF80*/

    /* enable I/O-space, memory-space, and bus mastering */

    EIEIO_SYNC;
    qspanAdr->pci_cs |= QSPAN_ENABLE_BM;	/*0x004*/
    EIEIO_SYNC;
}

/******************************************************************************
*
* qspanSpaceAccesses - enable the PCI access space
*
* This function enables I/O-space or memory-space
*
* RETURNS: N/A
*/

void qspanSpaceAccesses
	(
	PQSPAN 	qspanAdr,
	UINT8 	status
	)
{
	UINT32 Temp;
	UINT32 Base;

	if((status&PCI_CS_IOS)==PCI_CS_IOS)
	{	/*I/O space*/

		qspanAdr->qbsi1_ctl |= QBSI0_CTL_PAS;	/*0xF10*/

		qspanAdr->pci_cs &= (~PCI_CS_MS);
		qspanAdr->pci_cs |= PCI_CS_IOS;
	}
	else
	if((status&PCI_CS_MS)==PCI_CS_MS)
	{	/*MEM space*/
		qspanAdr->qbsi1_ctl &= (~QBSI0_CTL_PAS);

		qspanAdr->pci_cs |= PCI_CS_MS;
		qspanAdr->pci_cs &= (~PCI_CS_IOS);
	}
}

/******************************************************************************
*
* qspanBurstConfigure - enable/disable the PCI access Burst mode
*
* This function enable/disable the PCI access Burst mode
*
* RETURNS: N/A
*/
void qspanBurstConfigure
	(
	PQSPAN qspanAdr,
	UINT8 	image,
	UINT8	status
	)
{
	UINT32 Temp;
	/*enable the burst and the deep is 8 ×32 bit */

	if(image == QSPAN_PCI_CHNL0)
	{
		if(status==0x01)
		{
			/*the size of the cache line is 8*32 bit word*/
			qspanAdr->pci_misc0 = 0x00000008;
			
			qspanAdr->qbsi0_ctl |= QSPAN_QBSI_PWEN;
 		}
		else
		{
			qspanAdr->pci_misc0 = 0x00000000;
			qspanAdr->qbsi0_ctl &= (~QSPAN_QBSI_PWEN);
		}
	}
	else
	if(image == QSPAN_PCI_CHNL1)
	{
		if(status==0x01)
		{
			/*the size of the cache line is 8*32 bit word*/
			qspanAdr->pci_misc0 = 0x00000008;
			
			qspanAdr->qbsi1_ctl |= QSPAN_QBSI_PWEN;
 		}
		else
		{
			qspanAdr->pci_misc0 = 0x00000000;
			qspanAdr->qbsi1_ctl &= (~QSPAN_QBSI_PWEN);
		}
	}
}

/*************************************************************
*sysPCISpaceAssign- assign the PCI memory and IO space 
*
*
*
*/
void sysPCISpaceAssign()
{
	UINT8 temp;
	UINT32 BusNo,DevNo,FuncNo;
	PCI_HEADER_DEVICE *pPciDev;
	for(temp =0;temp<PCI_DEVICE_NUM;temp++)
	{
		pPciDev = (PCI_HEADER_DEVICE*)PCIDeviceTable[temp];
		/*pciFindDevice(pPciDev->vendorId,pPciDev->deviceId,0,&BusNo,&DevNo,&FuncNo);*/
		pciFindDevice(0x102c,0x00c0,0,&BusNo,&DevNo,&FuncNo);
		pciDevConfig(BusNo,DevNo,FuncNo,PCIDeviceBASE[temp][0],PCIDeviceBASE[temp][1],0x0002);
	}
}
/*************************************************************
*qspanPciConfigurationRead- Read the PCI Register value 
*
*
*
*/
UINT32 qspanPciConfigurationRead(
	PQSPAN qspan,
	UINT32 cycle_type,
	UINT32 bus_num,
	UINT32 dev_num,
	UINT32 func_num,
	UINT32 reg_num
	)
{
	UINT32 addr = 0;

	/*
	 * Setup Configuration Address Register
	 */

	addr = ((bus_num << 16) & CON_ADD_BUS) |
				((dev_num << 11) & CON_ADD_DEV) |
				((func_num << 8) & CON_ADD_FUNC) |
				((reg_num << 2) & CON_ADD_REG) |
				(cycle_type & CON_ADD_TYPE);

	qspan->con_add = addr;

	/* Read data from the specified PCI configuration register */
	return qspan->con_data;
}


/*************************************************************
*sysPCISpaceAssign- assign the PCI memory and IO space 
*
*
*
*/
void qspanIOControl
	(
	PQSPAN qspanAdr,
	UINT32 status
	)
{
	UINT32 Base;

	if((status&PCI_CS_IOS)==PCI_CS_IOS)
	{	/*I/O space*/

		qspanAdr->qbsi1_ctl |= QBSI0_CTL_PAS;

		qspanAdr->pci_cs &= (~PCI_CS_MS);
		qspanAdr->pci_cs |= PCI_CS_IOS;
		
	}
	else
	if((status&PCI_CS_MS)==PCI_CS_MS)
	{	/*MEM space*/
		qspanAdr->qbsi1_ctl &= (~QBSI0_CTL_PAS);

		qspanAdr->pci_cs &= (~PCI_CS_IOS);
		qspanAdr->pci_cs |= PCI_CS_MS;
	}

	/*Set the PCI Base address*/
	Base = qspanPciConfigurationRead((PQSPAN)qspanAdr,0,0,0,0,0x04);
	qspanAdr->qbsi1_at = ((Base&QBSI_AT_TA)|QBSI_AT_BS|QBSI_AT_EN);
}