u.c

大名鼎鼎的mpc8260的bsp源代码

	/*BR10(b0)<-0;  Return to normal byte register operation. */
     	}
 /**************************************************************** 
*  This routine  perform  u state transfer,it is a kernel functoin.
* Input:void
* Output: viod
*
ref:This is a ugly prototype
*****************************************************************/

 
 /**************************************************************** 
*  This routine  perform  u state transfer,it is a kernel functoin.
* Input:void
* Output: viod
*
ref:This is a test


		    b3                             b2                               b1                                 b0
NR0    SoftwareReset       PowerDown  Enable    Absolute PowerDown                  Return to Normal
NR1        Linkup	           Error Indication          Superframe Sync         Transparent Activation in Progress
NR2      ActivationRequest  Deactivation Request  Superframe Update Disable          Customer Enable
NR3 		IRQ3                             IRQ2                               IRQ1                             IRQ0
NR4       Enable IRQ3              Enable IRQ2                    Enable IRQ1                    Enable IRQ0
NR5       Reserved                        Block B1                     Block B2                      Swap B1/B2

*****************************************************************/
/*********************************************************************

BR0:M4 Transmit Data Register
BR1:M4 Receive  Data Register

M4 Bits        Network to NT                                            NT to Network
M40 (b7)              act  (0)                                                          act (0)
M41 (b6)              dea (1)                                                            ps1(1)
M42 (b5)              sco*  (1)                                                         ps2(1)
M43 (b4)              1**                                                            ntm(1)
M44 (b3)              1**                                                            cso(0)
M45 (b2)              1**                                                            1**
M46(b1)              [uoa]  (1)                                                          [sai](1)
M47 (b0)             [aib]    (1)                                                         nib*(1)
0111--1111							            0111--0111

LT------------------------>NT
act = start up bit, set = 0 during start up 
aib = alarm indication bit (set = 0 to indicate interruption) 
dea = turn off bit (set = 0 to indicate turn off) 1 = reserved bit for future standard (set = 1)
uoa = U–only–activation
sco = 0 start on command only

NT-------------------------> LT
act = start up bit, set = 1 during start up 
ntm =NT in test mode bit (set = 0 to indicate test mode)
cso = cold start only ( set = 1 for cold start only) 
ps1, ps2 = power status bits, (set = 0 to indicate power problems)
sai = S–activation indicator bit (optional, set = 1 for S/T activity)
 LinkActive 0 LinkActive 0nib = network indicator bit

***********************************************************************/



 void  NTISR0()
     	{
     		unsigned char  new_NR1 = 0x00;
     		unsigned char  BR1Val = 0x00;
     		unsigned char nr3Val;

             int intLevel = intLock();

     		nr3Val = scp_read_nr(0,U1NR3);

     		logMsg("u0 interrupt Enter here !\n",0,0,0,0,0,0);

     		if ((nr3Val & 0x08) == 0x08)
     			{
			new_NR1=scp_read_nr(0,U1NR1)&0x0F;
                		logMsg("IRQ3(NR1 modify) U0 -- NR1Val  = 0x%x\n",new_NR1,0,0,0,0,0);
		/*	if((new_NR1 & 0x0a )== 0xa || (new_NR1 & 0x0b) == 0xb ){*/
                   if((new_NR1  & 0x04) != 0x4){
   			scp_write_br(0,U1BR4,0x00);/* Clear febe counter */
			scp_write_br(0,U1BR5,0x00);/* Clear nebe counter */
			scp_write_br(0,U1BR0,0xf7);/*send AI*/
    			logMsg("U0 send AI!\n ",0,0,0,0,0,0);
				}
			
		/*	else if((new_NR1  & 0x04)== 0x4){	*/
                  else
                  {
			scp_write_nr(0,0x40);/*disable interrupt*/
			U0_state.LinkStatus = 5;
			
            /*HardwareLightOff(0);*/
    			logMsg("set EI !U0\n ",0,0,0,0,0,0);
    			Initial_U0();
    			return;  

    			#if 0
        		if((scp_read_nr(0,U1NR1)& 0x0f) == 0x4)
        			/*if(scp_read_nr(0,1)>>3 == 0)*/
        		    {
        			    scp_write_nr(0,0x28);
        			    return;  
        		    }
    			#endif
				 }
                   	/*	logMsg("U0 NR1Val  = 0x%x\n",new_NR1,0,0,0,0,0);*/
     			}
            
     		if((nr3Val & 0x02) == 0x02)
     			{
				
	     			BR1Val = scp_read_br(0,U1BR1)&0xFF;
                                logMsg(" IRQ1 (M buf modify) ---U0 --- BR1Val  = 0x%x\n",BR1Val,0,0,0,0,0);
	 			if( ((u0_glastBR1Val & 0x80) ==0x00) &&
	 				((BR1Val & 0x80) == 0x80) && 
	 				((BR1Val & 0x40) ==0x40) 
	 				) {
	 				scp_write_nr(0,0x21);
					U0_state.LinkStatus = 1;
                /*    HardwareLightOn(0);*/
	 			       logMsg(" Rev far end AI!,U0\n",0,0,0,0,0,0);
	 			}
	 			u0_glastBR1Val = BR1Val;

				}
            
         intUnlock (intLevel);
     	 }

       void  NTISR1()
     	{
     		unsigned char  new_NR1 = 0x00;
     		unsigned char  BR1Val = 0x00;
     		unsigned char nr3Val;
            
             int intLevel = intLock();
     		nr3Val = scp_read_nr(1,U1NR3);

         logMsg("u1 interrupt Enter here !\n",0,0,0,0,0,0);
     		
     		if ((nr3Val & 0x08) == 0x08)
     			{
        			new_NR1=scp_read_nr(1,U1NR1)&0x0F;
                               	logMsg("IRQ3(NR1 modify) U1-- NR1Val  = 0x%x\n",new_NR1,0,0,0,0,0);
			/*   if((new_NR1 & 0x0a )== 0xa || (new_NR1 & 0x0b) == 0xb ){*/
                          if((new_NR1  & 0x04) != 0x4){
           			scp_write_br(1,U1BR4,0x00);/* Clear febe counter */
        			scp_write_br(1,U1BR5,0x00);/* Clear nebe counter */
        			scp_write_br(1,U1BR0,0xf7);/*send AI*/
                          logMsg("U1 send AI!\n ",0,0,0,0,0,0);

        				}
			/*else if((new_NR1  & 0x04)== 0x4){	*/
                       else {
        			scp_write_nr(1,0x40);
        			U1_state.LinkStatus = 5;	
                  /*  HardwareLightOff(1);*/
            			logMsg("set EI !U1\n ",0,0,0,0,0,0);
        			Initial_U1();
        			return;  
        			#if 0
        		    if((scp_read_nr(1,1)& 0x08) == 0)
        		        {
            			/*if(scp_read_nr(1,1)>>3 == 0)*/
            			    scp_write_nr(1,0x28);
            			   return;   
        		        }
        		    #endif
            			
        			}
        		
            		/*	logMsg("U1 NR1Val  = 0x%x\n",new_NR1,0,0,0,0,0);*/
     			}

            
     		if((nr3Val & 0x02) == 0x02)
     			{
				
    	     			BR1Val = scp_read_br(1,U1BR1)&0xFF;
                                logMsg(" IRQ1 (M buf modify) ---U1 --- BR1Val  = 0x%x\n",BR1Val,0,0,0,0,0);
    	 			if( ((u1_glastBR1Val & 0x80) ==0x00) &&
    	 				((BR1Val & 0x80) == 0x80) && 
    	 				((BR1Val & 0x40) ==0x40) 
    	 				) {
    	 				scp_write_nr(1,0x21);
    					U1_state.LinkStatus = 1;	
                     /*   HardwareLightOn(1);*/
    	 			       logMsg(" Rev far end AI!,U1\n",0,0,0,0,0,0);
    	 			}
    	 			u1_glastBR1Val = BR1Val;

				}
            
            intUnlock (intLevel);
     	 }


 /**************************************************************** 
*  This routine active  u chip .
* Input:U_channel.0:U0 1:U1
* Output: viod
*****************************************************************/
    void HW_Active_U( unsigned char U_channel)
    	{
    
	/*WriteByte(U_FREQREF,U_channel);*//*select refqref 0:U0;1:u1*/
	if(U_channel == 0)
		{
		TSAINIT0(0);
		TSAINIT1(1);
		}
	else
		{
		TSAINIT0(1);
		TSAINIT1(0);
		}
	scp_write_nr(U_channel,0x28);	/* NR2(b3)<-1;Set activation request bit.*/

    	}


void SetUFreqref(unsigned char U_channel)
{
	WriteByte(U_FREQREF,U_channel);/*select refqref 0:U0;1:u1*/

}
 /**************************************************************** 
*  This routine get   u status .
* Input:U_channel.0:U0 1:U1
* Output: U status
*****************************************************************/

 LINK_STATUS *	HW_Get_U_State(unsigned char LinkId)
{

if(LinkId == 0)	
 return  &U0_state;
else if(LinkId == 1)
 return  &U1_state;


}

 /**************************************************************** 
*  This routine enable  u interface extern analog loopback .
* Input:U_channel.0:U0 1:U1
* Output: 
*****************************************************************/

 void ext_analog_loopback_en(unsigned char u_channel)
 	{
 	UCHAR tmp;
 	tmp = scp_read_br(u_channel,0x78);
 	tmp |=0x01;
 	scp_write_br(u_channel,0x78,tmp);/*br8(b0)<---1*/
 	taskDelay(10);/*wait for 5 sce*/
 	scp_write_or(u_channel,0x78,0x22);/*or8=0x22*/
 	scp_write_or(u_channel,0x79,0x20);/*or9 = 0x20*/

 	}
 /**************************************************************** 
*  This routine disable  u interface extern analog loopback .
* Input:U_channel.0:U0 1:U1
* Output: 
*****************************************************************/

 void ext_analog_loopback_dis(unsigned char u_channel)
 	{
 	 	UCHAR tmp;

 	scp_write_or(u_channel,0x78,0x22);/*or8=0x00*/
 	scp_write_or(u_channel,0x79,0x20);/*or9 = 0x00*/
 	
 	tmp = scp_read_br(u_channel,0x78);
 	tmp |=0xfe;
 	scp_write_br(u_channel,0x78,tmp);/*br8(b0)<--0*/

 	}


 /**************************************************************** 
*  This routine enable  u interface super frame and deframe  loopback .
* Input:U_channel.0:U0 1:U1
* Output: 
*****************************************************************/

void u_super_frame_deframe_loopback(unsigned char u_channel)
{
UCHAR tmp;
tmp = scp_read_br(u_channel,0x78);
tmp |=0x01;
scp_write_br(u_channel,0x78,tmp);/*br8(b0)<---1*/

taskDelay(10);/*wait for 5 sce*/

scp_write_br(u_channel,0x7e,0x10);/*br14=0x10*/
scp_write_br(u_channel,0x78,0xb7);/*br8=0xb7*/

scp_write_br(u_channel,0x7c,0x89);/*br12=0x89*/
scp_write_br(u_channel,0x7d,0x0c);/*br13=0x0c*/
scp_write_nr(u_channel,0x21);/*nr2=0x01*/

}
  /**************************************************************** 
*  This routine disable  u interface super frame and deframe  loopback .
* Input:U_channel.0:U0 1:U1
* Output: 
*****************************************************************/

void u_super_frame_deframe_loopback_dis(unsigned char u_channel)
{

scp_write_br(u_channel,0x7e,0x0);/*br14=0x0*/
scp_write_br(u_channel,0x78,0x0);/*br8=0x0*/

scp_write_br(u_channel,0x7c,0x0);/*br12=0x0*/
scp_write_br(u_channel,0x7d,0x0);/*br13=0x0c*/

}
 /**************************************************************** 
*  This routine enable  u interface LDL2  loopback .
* Input:U_channel.0:U0 1:U1
* Output: 
*****************************************************************/
void IDL2_loopback(unsigned char u_channel)
{
UCHAR tmp;
tmp=scp_read_br(u_channel,0x76);
tmp |=0x02;
scp_write_br(u_channel,0x76,tmp);/*br6(b1)<----1*/

}

void HW_UChannel_Select(unsigned  char U_channel )
{
#if 0
    if(U_channel >1 ) return;
		/*the block select u chip channel 
		 1 byte pre 2 bit means 1 u channel ie.
		 FR_U_Channel_Sel[1:0] == 10 means selected u0 chip b1 channel,else not selected u0b1
		 FR_U_Channel_Sel[3:2] == 10 means selected u0 chip b2 channel,else not selected u0b2
		 FR_U_Channel_Sel[5:4] == 10 means selected u1 chip b1 channel,else not selected u1b1
		 FR_U_Channel_Sel[7:6] == 10 means selected u1 chip b2 channel,else not selected u1b2
		*/
    	if(U_channel == 0)
    		WriteByte(FR_U_Channel_Sel,0xfa);/*turn on  U chip channel: u0 b1 b2 voice channel */
    	else if(U_channel == 1)
    		WriteByte(FR_U_Channel_Sel,0xaf);/*turn on  U chip channel: u1 b1 b2 voice channel*/

#endif
    		WriteByte(FR_U_Channel_Sel,0xfa);/*turn on  U chip channel: u0/u1 b1 b2 voice channel */
        
	}