u.c

大名鼎鼎的mpc8260的bsp源代码

#include "Mc145572.h"
#include "vxWorks.h"
#include "intLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "arch/ppc/vxPpcLib.h"

#include "drv/multi/ppc860Siu.h"

#include  "drv/intrCtl/ppc860Intr.h" 
#include  "arch/ppc/ivPpc.h" 

#include "fpga.h"
#include "Ads860.h"


/*--------------- Global varible ------------------------*/


     	unsigned char  u0_glastBR1Val = 0xfe;
     	unsigned char  u1_glastBR1Val = 0xfe;
         LINK_STATUS  U0_state ,U1_state;
         

void HardwareLightOn(unsigned char U_channel)
{
  int immrVal = INTERNAL_MEM_MAP_ADDR;	
  if(U_channel == 0)
  {
  /* uuuu_uuuu_uuuu_0uuu*/
  *PCPAR(immrVal) &= ~0x0008;/*pcpar_12<---0*/
  /* uuuu_uuuu_uuuu_1uuu*/
  *PCDIR(immrVal)  |= 0x0008;  /*pcdir12<---1*/
  /* uuuu_uuuu_uuuu_1uuu*/
  *PCDAT(immrVal)  |= 0x0008;/*padat12<---1*/
  	
    }
    else if(U_channel == 1)
    {

  /* uuuu_uuuu_uuuu_u0uu*/
  *PCPAR(immrVal) &= ~0x0004;/*pcpar_13<---0*/
  /* uuuu_uuuu_uuuu_u1uu*/
  *PCDIR(immrVal)  |= 0x0004;  /*pcdir13<---1*/
  /* uuuu_uuuu_uuuu_u1uu*/
  *PCDAT(immrVal)  |= 0x0004;/*padat13<---1*/

    }
	
	
}
void HardwareLightOff(unsigned char U_channel)
{
  int immrVal = INTERNAL_MEM_MAP_ADDR;	
	
  if(U_channel == 0)
  {
  /* uuuu_uuuu_uuuu_0uuu*/
  *PCPAR(immrVal) &= ~0x0008;/*pcpar_12<---0*/
  /* uuuu_uuuu_uuuu_1uuu*/
  *PCDIR(immrVal)  |= 0x0008;  /*pcdir12<---1*/
  /* uuuu_uuuu_uuuu_0uuu*/
  *PCDAT(immrVal)  &= ~0x0008;/*padat12<---0*/
  	
    }
    else if(U_channel == 1)
    {

  /* uuuu_uuuu_uuuu_u0uu*/
  *PCPAR(immrVal) &= ~0x0004;/*pcpar_13<---0*/
  /* uuuu_uuuu_uuuu_u1uu*/
  *PCDIR(immrVal)  |= 0x0004;  /*pcdir13<---1*/
  /* uuuu_uuuu_uuuu_u0uu*/
  *PCDAT(immrVal)  &=~0x0004;/*padat13<---0*/

    }
}

#if 0
void HardwareResetU(unsigned char U_channel)

{
   int immrVal = INTERNAL_MEM_MAP_ADDR;

	
   *PDPAR(immrVal) &= ~0x0030;
   *PDDIR(immrVal)  |= 0x0030;  

   if(U_channel == 0)
    {
   *PDDAT(immrVal) &= ~0x0020; /*pd10 <---0 for U(Mc145572) reset*/
    taskDelay(10);
   *PDDAT(immrVal) |= 0x0020; /*pd10 <---1*/ 
    }
   else if(U_channel == 1)
    {
   *PDDAT(immrVal) &= ~0x0010; /*pd11 <---0 for U(Mc145572) reset*/
    taskDelay(10);
   *PDDAT(immrVal) |= 0x0010; /*pd11 <---1*/   
    }

}
#endif
 void  SoftResetU(unsigned char U_channel)
    {

    	scp_write_nr(U_channel,0x08);

    	/*NR0(b3)<-1;Assert software reset. Only requiredat power–up initialization.	*/
    	scp_write_nr(U_channel,0x00);
    	/* NR0(b3)<-0;De–assert software reset. Only required at power–up initialization.*/

    }

void PrepareUInt(void)
{
intConnect (IV_IRQ4, (VOIDFUNCPTR)NTISR0,  0);
intEnable (IVEC_TO_INUM(IV_IRQ4));
intConnect (IV_IRQ5, (VOIDFUNCPTR)NTISR1,  0);
intEnable (IVEC_TO_INUM(IV_IRQ5));

}
/**************************************************************** 
*  This routine initializes the U chip to the operational state.
* Input:U_channel 0:u0 1;u1
* Output: viod
*****************************************************************/
 void  HW_NT_Initial(unsigned char U_channel)
{
    	SoftResetU(U_channel);
    	
	  	 if(U_channel == 0)  
		{
		Initial_U0();
		/* TSAINIT0(0);*/
		U0_state.LinkStatus = 0xfe;
		}
		else if(U_channel == 1)
		{
		Initial_U1();
	     /* TSAINIT1(1);*/
		U1_state.LinkStatus = 0xfe;
		}
		
	 
}

/**************************************************************** 
*  This routine initializes the U chip to the operational state.
* Input:U_channel 0:u0 1;u1
* Output: viod
*****************************************************************/
 void  Initial_U0(void)
 	{
        unsigned char tmp = 0;
        int i = 0;
	scp_write_br(0,0x70,0x77);

	/* M4 transmit: act = 0, power normal, normal mode (ntm = 1), warm start
	capable, unused bits = 1 */
	scp_write_br(0,0x71,0x7F);
	/* Set initial conditions on M4 channel receive. This (BR0 = 7F) will
	force an M channel interrupt to occur when the M4 act bit from the LT
	changes from a 0 to a 1, signifying Layer 2 communication readiness*/
	
	scp_write_br(0,0x72,0xF0);
	/* M5 and M6 channels to ANSI T1.601–1992 reserved condition. febe Input= 1. */

	scp_write_br(0,0x79,0x1c);
	/* Select automatic eoc mode, M4 dual consecutive check, M5/M6 update on
	every frame and transmitted febe is computed nebe. */
	
/*modify begin  2004.2.28*/
    #if 0
	scp_write_or(0,0x77,0x01);
    #else

    /*br7(b2) = 1 select clock rate is 2.048Mhz;
    br7(b0) =0 select idl2 8bit mode, but is ignored after timeslot assignment mode is enable  */
    	tmp=scp_read_br(0,0x77);
	tmp |=0x05;
	scp_write_br(0,0x77,tmp);/*br7(b2,b0)<---1*/

    /************   select or --> after opertion for or***************/
      	/*BR10(b0)<-1; Select init group registers. */
	scp_write_br(0,0x7a,0x01);
        for(i=0;i<1000;i++);
    
    	/*OR7(b0)<-1; Enable trinal checking of M4 act, dea, and uoa bits. The remaining M4
	bits are dual consecutive checked as defined in BR9(b4:b5) */

       scp_write_br(0,0x77,0x01); /*OR7(b0)<-1;or7(b4)<---0    */
       /*or7(b4)=0 and br7(b2) = 1 select clock rate 2.048Mhz*/


	tmp=scp_read_br(0,0x78);
	tmp |=0x10;
	scp_write_br(0,0x78,tmp);/*or8(b4)<---1  FREQREF output enable */



    	/*BR10(b0)<-0;*/ /* Return to normal byte register operation. select br*/
	
	scp_write_br(0,0x7a,0x00);
      for(i=0;i<1000;i++);

    #endif


/*modify end  2004.2.28*/

	
		
	scp_write_nr(0,0x4a);

	/* NR4<-A;Enable IRQ3, activation/D channel interrupt and IRQ1 – M4 Channel
	interrupt. */
	/*taskDelay(5);*/

 	}


 void  Initial_U1(void)
 	{
        unsigned char tmp = 0;
        int i = 0;
	scp_write_br(1,0x70,0x77);

	/* M4 transmit: act = 0, power normal, normal mode (ntm = 1), warm start
	capable, unused bits = 1 */
	scp_write_br(1,0x71,0x7F);
	/* Set initial conditions on M4 channel receive. This (BR0 = 7F) will
	force an M channel interrupt to occur when the M4 act bit from the LT
	changes from a 0 to a 1, signifying Layer 2 communication readiness*/
	
	scp_write_br(1,0x72,0xF0);
	/* M5 and M6 channels to ANSI T1.601–1992 reserved condition. febe Input= 1. */

	scp_write_br(1,0x79,0x1c);
	/* Select automatic eoc mode, M4 dual consecutive check, M5/M6 update on
	every frame and transmitted febe is computed nebe. */

/*modify begin  2004.2.28*/
    #if 0
	scp_write_or(1,0x77,0x01);
    #else

    /*br7(b2) = 1 select clock rate is 2.048Mhz;
    br7(b0) =0 select idl2 8bit mode, but is ignored after timeslot assignment mode is enable  */
    	tmp=scp_read_br(1,0x77);
	tmp |=0x05;
	scp_write_br(1,0x77,tmp);/*br7(b2,b0)<---1*/

    /************   select or --> after opertion for or***************/
      	/*BR10(b0)<-1; Select init group registers. */
	scp_write_br(1,0x7a,0x01);
        for(i=0;i<1000;i++);
    
    	/*OR7(b0)<-1; Enable trinal checking of M4 act, dea, and uoa bits. The remaining M4
	bits are dual consecutive checked as defined in BR9(b4:b5) */

       scp_write_br(1,0x77,0x01); /*OR7(b0)<-1;or7(b4)<---0    */
       /*or7(b4)=0 and br7(b2) = 1 select clock rate 2.048Mhz*/


	tmp=scp_read_br(1,0x78);
	tmp |=0x10;
	scp_write_br(1,0x78,tmp);/*or8(b4)<---1  FREQREF output enable */



    	/*BR10(b0)<-0;*/ /* Return to normal byte register operation. select br*/
	
	scp_write_br(1,0x7a,0x00);
      for(i=0;i<1000;i++);

    #endif


/*modify end  2004.2.28*/
		
	scp_write_nr(1,0x4a);

	/* NR4<-A;Enable IRQ3, activation/D channel interrupt and IRQ1 – M4 Channel
	interrupt. */
	taskDelay(5);

 	}


/**************************************************************** 
*  This routine perform u1 chip time salot assign.
* Input:void
* Output: viod
*****************************************************************/
     void  TSAINIT0(unsigned char U_channel)
     	{
	scp_write_br(U_channel,0x7a,0x01);
	/*BR10(b0)<-1; Select init group registers. */
	scp_write_br(U_channel,0x70,0x00);
	/*  OR0<-0x00;B1 of U1  transmit starts in TS0 */
	scp_write_br(U_channel,0x71,0x04);
	/*OR1<-0x04; B2 of U1 transmit starts in TS4*/
	scp_write_br(U_channel,0x72,0x10);
	/*OR2<-0x10; D  of U1 transmit starts in TS16 */
	scp_write_br(U_channel,0x73,0x00);
	/*OR3<-0x00; B1of U1  receive starts in TS0 */
	scp_write_br(U_channel,0x74,0x04);
	/*OR4<-0x04; B2 of U1  receive starts in TS4 */
	scp_write_br(U_channel,0x75,0x10);
	/*OR5<-0x10; D of U1 receive is in TS16 */	
	#if 1
	scp_write_br(U_channel,0x77,0x20);
	
	scp_write_br(U_channel,0x78,0x08);
	#endif

	
	scp_write_br(U_channel,0x76,0xE0);
	/*OR6<-0xE0; Enable u0 B1, B2, and D of U1 timeslots.*/
	
	
	scp_write_br(U_channel,0x7a,0x00);
	/*BR10(b0)<-0;  Return to normal byte register operation. */
     	}
 /**************************************************************** 
*  This routine perform u2 chip time salot assign.
* Input:void
* Output: viod
*****************************************************************/
 	void  TSAINIT1(unsigned char U_channel)
     	{
	scp_write_br(U_channel,0x7a,0x01);
	/*BR10(b0)<-1; Select init group registers. */
	scp_write_br(U_channel,0x70,0x08);
	/*  OR0<-0x00;B1 of U1  transmit starts in TS0 */
	scp_write_br(U_channel,0x71,0x0c);
	/*OR1<-0x04; B2 of U1 transmit starts in TS4*/
	scp_write_br(U_channel,0x72,0x11);
	/*OR2<-0x10; D  of U1 transmit starts in TS13 */
	scp_write_br(U_channel,0x73,0x08);
	/*OR3<-0x00; B1of U1  receive starts in TS0 */
	scp_write_br(U_channel,0x74,0x0c);
	/*OR4<-0x04; B2 of U1  receive starts in TS4 */
	scp_write_br(U_channel,0x75,0x11);

	#if 1
	scp_write_br(U_channel,0x77,0x20);
	
	scp_write_br(U_channel,0x78,0x08);
	#endif
	/*OR5<-0x10; D of U1 receive is in TS13 */	
	scp_write_br(U_channel,0x76,0xE0);

	/*OR6<-0xE0; Enable B1, B2, and D of U1 timeslots.*/
	scp_write_br(U_channel,0x7a,0x00);