rominit.s

来自「大名鼎鼎的mpc8260的bsp源代码」· S 代码 · 共 546 行 · 第 1/2 页

	stw     r5, MSTAT(0)(r4)

	/*mamr */

	lis     r5, HIADJ (0x9c124111)
        addi    r5, r5,LO (0x9c124111)        
	 stw     r5, MAMR(0)(r4)

	/* it has to be the divide by 16 */

	li	r6, 0x0400 
 

	/* program the MPTPR */

	sth	r6, MPTPR(0)(r4)
 
        /*
         * load r6/r7 with the start/end address of the UPM table for an
         * SDRAM @ 50MHZ.
         */

        lis     r6, HIADJ( upmInitSdram)
        addi    r6, r6, LO(upmInitSdram)
        lis     r7, HIADJ( upmInitSdramEnd)
        addi    r7, r7, LO(upmInitSdramEnd)
 
        /* init UPMB for memory access */
 
        sub     r5, r7, r6              /* compute table size */
        srawi   r5, r5, 2               /* in integer size */
 
        /* convert UpmTable to ROM based addressing */
 
        lis     r7, HIADJ(romInit)
        addi    r7, r7, LO(romInit)
 
        lis     r8, HIADJ(ROM_TEXT_ADRS)
        addi    r8, r8, LO(ROM_TEXT_ADRS)
 
        sub     r6, r6, r7              /* subtract romInit base address */
        add     r6, r6, r8              /* add in ROM_TEXT_ADRS address */
 
        lis     r9, HIADJ (MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)
        addi    r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)
 
UpmbWriteLoop:
        /* write the UPM table in the UPM */
 
        lwz     r10, 0(r6)              /* get data from table */
        stw     r10, MDR(0)(r4)         /* store the data to MD register */
 
        stw     r9, MCR(0)(r4)          /* issue command to MCR register */
 
        addi    r6, r6, 4               /* next entry in the table */
        addi    r9, r9, 1               /* next MAD address */


        addi    r5,r5,-1
        cmpwi   r5,0
        bne     UpmbWriteLoop

 
        /* 
	 * Configure the 32 bit address to be output on the address bus 
	 * if AMX = 0xb11.
         * See section 16.6.4.1 "Arm Words".  The following values must 
	 * be placed on the defined SDRAM address pins:
         *   A[9]   = 0          burst write mode
         *   A[6:4] = 010        cas latency of two
         *   A[3]   = 0          sequential mode
         *   A[2:0] = 010        burst length 4
         *
         * The address must be shifted left by 2 bits for 32 bit wide SDRAM...
         *   (0b0100010 << 2) = 0x88
         */

        lis     r5, HIADJ(0x02000088)
        addi    r5, r5, LO(0x02000088)
        stw     r5, MAR(0)(r4)
 
 

        /* 
	 * issue a mode register set (MRS) to initialize the SDRAM mode 
	 * register.  This programs the burst length, CAS latency and 
	 * write mode. Run MRS pattern from UPMB location 8.
         */

        lis     r5, HIADJ(0x8000ea08)
        addi    r5, r5, LO(0x8000ea08)
        stw     r5, MCR(0)(r4)

        lis     r5, HIADJ(0x8000ea08)
        addi    r5, r5, LO(0x8000ea08)
        stw     r5, MCR(0)(r4)





        /*
         * load r6/r7 with the start/end address of the UPM table for an
         * SDRAM @ 50MHZ.
         */

        lis     r6, HIADJ( upmbTableSdram)
        addi    r6, r6, LO(upmbTableSdram)
        lis     r7, HIADJ( upmbTableSdramEnd)
        addi    r7, r7, LO(upmbTableSdramEnd)
 
        /* init UPMB for memory access */
 
        sub     r5, r7, r6              /* compute table size */
        srawi   r5, r5, 2               /* in integer size */
 
        /* convert UpmTable to ROM based addressing */
 
        lis     r7, HIADJ(romInit)
        addi    r7, r7, LO(romInit)
 
        lis     r8, HIADJ(ROM_TEXT_ADRS)
        addi    r8, r8, LO(ROM_TEXT_ADRS)
 
        sub     r6, r6, r7              /* subtract romInit base address */
        add     r6, r6, r8              /* add in ROM_TEXT_ADRS address */
 
        lis     r9, HIADJ (MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)
        addi    r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)

UpmbWriteLoop1:
        /* write the UPM table in the UPM */
 
        lwz     r10, 0(r6)              /* get data from table */
        stw     r10, MDR(0)(r4)         /* store the data to MD register */	
 
        stw     r9, MCR(0)(r4)          /* issue command to MCR register */
 
        addi    r6, r6, 4               /* next entry in the table */
        addi    r9, r9, 1               /* next MAD address */


        addi    r5,r5,-1
        cmpwi   r5,0
        bne     UpmbWriteLoop1
	


	lis     r5, HIADJ (0x9c924111)
        addi    r5, r5,LO (0x9c924111)
        stw     r5, MAMR(0)(r4)


	/* set the SPLL frequency */

	lis	r5, HIADJ( 0x00000000)
	addi	r5, r5, LO(0x00000000)
	stw	r5, PLPRCR(0)(r4)


        /* initialize the stack pointer */
	lis	sp, HIADJ(STACK_ADRS)
	addi	sp, sp, LO(STACK_ADRS)
	
     

	/* go to C entry point */

	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */
  #if 1  /*Light*/

	li	r5, 0x0000
	sth	r5, PAPAR(0)(r4)

	li	r5, 0x0500
	sth	r5, PADIR(0)(r4)
	
	li	r5, 0x0500
	sth	r5, PADAT(0)(r4)
	
	li	r5, 0x4000
loop2:
	addi	r5,  r5, -1
	cmpwi	r5,  0
	bne	loop2
	
/*	b loop0*/
#endif

	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: romStart - R7 + R8 
	 */

        lis	r6, HIADJ(romStart)	
        addi	r6, r6, LO(romStart)	/* load R6 with C entry point */

	sub	r6, r6, r7		/* routine - entry point */
	add	r6, r6, r8 		/* + ROM base */

	mtlr	r6			/* move C entry point to LR */
	blr				/* jump to the C entry point */



/* This 50 MHz SDRAM table is for...
 *   860EN Rev B.1 9829 and newer silicon
 *   860T  Rev B.3 9832 and newer silicon
 *
 * This table will NOT work with older 860EN or 860T parts.
 */



upmInitSdram:
 
/* single read   (offset 0x00 in upm ram) */
       .long   0xfffffc04, 0x0f0cfc04, 0x0ffffc04, 0x01bf7004
       .long   0x0ffdd000, 0x1ffff447, 0x0ffffc04, 0x1ffffc07
/* burst read    (offset 0x08 in upm ram) */
       .long   0xfffff004, 0x0ffcc004, 0xfffff004, 0xfffff034
       .long   0x0fac0034, 0xfffff004, 0xfffff004, 0x0ffc3084
       .long   0xfffff004, 0xfffff004, 0xfffff004, 0xfffff004
       .long   0xfffff084, 0xfffff407, 0xfffffc04, 0xfffffc04
/* single write  (offset 0x18 in upm ram) */
       .long   0xfffffc04, 0xfffffc04, 0x0f0cfc04, 0x0ffff800
       .long   0x00af0004, 0x1ffdd447, 0xfffffc44, 0xfffffc47
/* burst write   (offset 0x20 in upm ram) */
       .long   0xfffffc04, 0xfffffc04, 0x0f0cfc04, 0x0ffff800
       .long   0x00ff0000, 0x00fff000, 0x00fff000, 0x00fff004
       .long   0x11fff447, 0xfffffc47, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* refresh       (offset 0x30 in upm ram) */
       .long   0xeffeb804, 0x0ffc3004, 0xfffff004, 0xfffff004
       .long   0xfffff447, 0xfffffc07, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* exception     (offset 0x3C in upm ram) */
       .long   0xfffffc07, 0xfffffc07, 0xfffffcff, 0xfffffcff
 
upmInitSdramEnd:

 
upmbTableSdram:
 
/* single read   (offset 0x00 in upm ram) */
       .long   0xfffffc04, 0x0f0cfc04, 0x0ffff804, 0x01bf7004
       .long   0x0ffdd000, 0x1ffff447, 0x0ffffc04, 0x1ffffc07
/* burst read    (offset 0x08 in upm ram) */
       .long   0xfffffc04, 0x0f0cfc04, 0x0ffff804, 0x00ff3004
       .long   0x00fff000, 0x00fff000, 0x00fff000, 0x00fff000
       .long   0x00fff000, 0x11fff447, 0xfffffc47, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* single write  (offset 0x18 in upm ram) */
       .long   0xfffffc04, 0xfffffc04, 0x0f0cfc04, 0x0ffff800
       .long   0x00af0004, 0x1ffdd447, 0xfffffc44, 0xfffffd47
/* burst write   (offset 0x20 in upm ram) */
       .long   0xfffffc04, 0xfffffc04, 0x0f0cfc04, 0x0ffff800
       .long   0x00ff0000, 0x00fff000, 0x00fff000, 0x00fff004
       .long   0x11fff447, 0xfffffc47, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* refresh       (offset 0x30 in upm ram) */
       .long   0xeffeb804, 0x0ffc3004, 0xfffff004, 0xfffff004
       .long   0xfffff447, 0xfffffc07, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* exception     (offset 0x3C in upm ram) */
       .long   0xfffffc07, 0xfffffc07, 0xfffffcff, 0xfffffcff
 
upmbTableSdramEnd: