rominit.s

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/* romInit.s - Motorola 860ads ROM initialization module */

/* Copyright 1984-1996 Wind River Systems, Inc. */
	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river

/*
modification history
--------------------
01m,26jan99,cn   added  support  for SDRAM (SPR# 24337). Also removed checks 
		 to BCSR2_DRAM_NO_EDO_L and BCSR2_DRAM_EDO_L as this bit 
		 is not actually implemented.  
01l,09nov98,cn   added support for FADS860T boards.
01k,30jul98,gls  fixed to initialize CS0/CS1 earlier to allow access to BCSR3
01j,18feb98,gls	 added support for PPC823FADS
01i,23jun97,map  fixed MAMR init for 16/32 DRAM [SPR# 8753]
01h,17dec96,tpr  fixed MAMR init. bug with 16 and 32 Mbytes dram (SPR #7661)
01g,10nov96,tpr  updated UPM table. 
		 removed RTCSC initialization.
01f,08nov96,tpr  modified UPM table for EDO Dram @ 50 Mhz.
01e,06nov96,tpr  replaced PLPRCR_MF_SFT by PLPRCR_MF_SHIFT.
01d,06nov96,tpr  Clean up the code (SPR #7336).
		 added DRAM speed selection (SPR #7335).
01c,24jun96,tpr  Reworked all initialization code.
01b,04jun96,cah  Add mem controller minimal init sequence
01a,19apr96,tpr  written.
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"	
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"

	/* internals */

	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */
	
	/* externals */

	.extern romStart	/* system initialization routine */

	.text
	.align 2
	

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/

_romInit:
romInit:
	bl	cold		/* jump to the cold boot initialization */
	
	bl	start		/* jump to the warm boot initialization */

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "GDT. FEC"
	.align 2

cold:
	li	r3, BOOT_COLD	/* set cold boot as start type */

	/*
	 * When the PowerPC 860 is powered on, the processor fletch the
	 * instructions located at the address 0x100. We need to jump
	 * from the address 0x100 to the Flash space.
	 */

	lis	r4, HIADJ(start)		/* load r4 with the address */
	addi	r4, r4, LO(start)		/* of start */

	lis	r5, HIADJ(romInit)		/* load r5 with the address */
	addi	r5, r5, LO(romInit)		/* of romInit() */

	lis	r6, HIADJ(ROM_TEXT_ADRS)	/* load r6 with the address */
	addi	r6, r6, LO(ROM_TEXT_ADRS)	/* of ROM_TEXT_ADRS */

	sub	r4, r4, r5			/*  */
	add	r4, r4, r6 

	mtspr	LR, r4				/* save destination address*/
						/* into LR register */
	blr					/* jump to flash mem address */
			
start:
	/* set the MSR register to a known state */

	xor	r4, r4, r4		/* clear register R4 */
	mtmsr 	r4			/* cleat the MSR register */

	/* DER - clear the Debug Enable Register */

	mtspr	DER, r4

	/* ICR - clear the Interrupt Cause Register */

	mtspr	ICR, r4

	/* 
	 * ICTRL - initialize the Intstruction Support Control register
	 *	   
	 */

	lis	r5, HIADJ(0x00000007)
	addi	r5, r5, LO(0x00000007)
	mtspr	ICTRL, r5

	/* disable the instruction/data cache */
	
	lis	r4, HIADJ ( CACHE_CMD_DISABLE)		/* load disable cmd */
	addi	r4, r4, LO (CACHE_CMD_DISABLE)
	mtspr	IC_CST, r4				/* disable I cache */
	mtspr	DC_CST, r4				/* disable D cache */

	/* unlock the instruction/data cache */

	lis	r4, HIADJ ( CACHE_CMD_UNLOCK_ALL)	/* load unlock cmd */
	addi	r4, r4, LO (CACHE_CMD_UNLOCK_ALL)
	mtspr	IC_CST, r4			/* unlock all I cache lines */
	mtspr	DC_CST, r4			/* unlock all D cache lines */

	/* invalidate the instruction/data cache */

	lis	r4, HIADJ (CACHE_CMD_INVALIDATE)   /* load invalidate cmd*/
	addi	r4, r4, LO (CACHE_CMD_INVALIDATE)
	mtspr	IC_CST, r4		/* invalidate all I cache lines */
	mtspr	DC_CST, r4		/* invalidate all D cache lines */

	/*
	 * initialize the IMMR register before any non-core registers
	 * modification.
	 */

	lis	r4, HIADJ( INTERNAL_MEM_MAP_ADDR)	
	addi	r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
	mtspr	IMMR, r4		/* initialize the IMMR register */

	mfspr	r4, IMMR		/* read it back, to be sure */
	rlwinm  r4, r4, 0, 0, 15	/* only high 16 bits count */

	/* SYPCR - turn off the system protection stuff */
	
	lis	r5, HIADJ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
	addi	r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
	stw	r5, SYPCR(0)(r4)
	
	lis	r6, HIADJ(SIUMCR_DLK  | SIUMCR_DPC | \
			SIUMCR_MLRC_KR | SIUMCR_SEME | SIUMCR_GB5E )
	addi	r6, r6, LO( SIUMCR_DLK  | SIUMCR_DPC | \
			SIUMCR_MLRC_KR | SIUMCR_SEME | SIUMCR_GB5E )
	lwz	r5, SIUMCR(0)(r4)
	or	r5, r5, r6
	stw	r5, SIUMCR(0)(r4)

	/* set PIT status and control init value */

	li	r5, PISCR_PS | PISCR_PITF
	sth	r5, PISCR(0)(r4)
	
	/*
	 * Map the bank 0 to the flash area - On the ADS board at reset time
	 * the bank 0 is already used to map the flash.
	 */
	 
/* Map  the bank  to the bootrom */	 
	lis	r5, HIADJ( 0x02800401)
	addi	r5, r5, LO(0x02800401)
	stw	r5, BR0(0)(r4)

	lis	r5, HIADJ(0xffe00950)
	addi	r5, r5, LO(0xffe00950)
	stw	r5, OR0(0)(r4)

/* Map  the bank  to the flash */

	lis	r5, HIADJ( 0xff000980)
	addi	r5, r5, LO( 0xff000980)
	stw	r5, OR1(0)(r4)

	lis	r5, HIADJ( 0x30000401)
	addi	r5, r5, LO(0x30000401)
	stw	r5, BR1(0)(r4)

/* Map  the bank  to the SRAM */
	
	
	lis	r5, HIADJ( 0xffe00950)
	addi	r5, r5, LO(0xffe00950)
	stw	r5, OR2(0)(r4)

	lis	r5, HIADJ( 0x40000001)
	addi	r5, r5, LO(0x40000001)
	stw	r5, BR2(0)(r4)
	
/* Map  the bank  to the FPGA */
	
	
	lis	r5, HIADJ( 0xf00009a0)
	addi	r5, r5, LO(0xf00009a0)
	stw	r5, OR3(0)(r4)

	lis	r5, HIADJ( 0x50000401)
	addi	r5, r5, LO(0x50000401)
	stw	r5, BR3(0)(r4)
	
/* Map  the bank  to the Qspan */

	lis	r5, HIADJ( 0xffff0948)
	addi	r5, r5, LO(0xffff0948)
	stw	r5, OR5(0)(r4)

	lis	r5, HIADJ( 0x70000001)
	addi	r5, r5, LO( 0x70000001)
	stw	r5, BR5(0)(r4) 
	
/* Map  the bank  to the CT69000 */

	lis	r5, HIADJ( 0xf0000948)
	addi	r5, r5, LO(0xf0000948)
	stw	r5, OR6(0)(r4)

	lis	r5, HIADJ( 0x80000001)
	addi	r5, r5, LO( 0x80000001)
	stw	r5, BR6(0)(r4) 
	
/* Map  the bank  to the SDRAM */

	lis	r5, HIADJ( 0xfe000200)
	addi	r5, r5, LO(0xfe000200)
	stw	r5, OR7(0)(r4)

	lis	r5, HIADJ( 0x00000081)
	addi	r5, r5, LO( 0x00000081)
	stw	r5, BR7(0)(r4)
	
	/* TBSCR - initialize the Time Base Status and Control register */

	lis	r5, HIADJ( TBSCR_REFA | TBSCR_REFB)
	addi	r5, r5, LO(TBSCR_REFA | TBSCR_REFB)
	sth	r5, TBSCR(0)(r4)	

	/*mstat */

        lis     r5, HIADJ (0x00000000)
        addi    r5, r5,LO (0x00000000)