pciconfig.h

来自「大名鼎鼎的mpc8260的bsp源代码」· C头文件 代码 · 共 380 行 · 第 1/2 页

#define QSPAN_CLR_QEL_IS	0x40000000 /* QBus error log interrupt status */
#define QSPAN_CLR_DPD_IS	0x20000000 /* data parity interrupt status */
#define QSPAN_CLR_IPE_IS	0x08000000 /* IDMA PCI error interrupt status */
#define QSPAN_CLR_IQE_IS	0x04000000 /* IDMA QBus error int. status */
#define QSPAN_CLR_IRST_IS	0x02000000 /* IDMA reset interrupt status */
#define QSPAN_CLR_DONE_IS	0x01000000 /* IDMA done interrupt status */
#define QSPAN_CLR_SI1_IS	0x00000002 /* Software interrupt 1 status */
#define QSPAN_CLR_SI0_IS	0x00000001 /* Software interrupt 0 status */
#define QSPAN_CLR_IRST		0x00400000 /* clear the IDMA reset status */
#define QSPAN_CLR_DONE		0x00200000 /* clear the IDMA Done status */
#define QSPAN_CLR_IPE		0x00100000 /* clear the IDMA PCI error status */
#define QSPAN_CLR_IQE		0x00080000 /* clear the IDMA Qbus err. status */
#define QSPAN_SET_IMODE		0x00000008 /* set IDMA transfer for MBX */

/* size in bytes of QSPAN register space */

#define QSPAN_REG_SIZE	0x1000	/* 4KB register space */


#define PCI_CS_MS				0x00000002		/*MEMORY SPACE*/
#define PCI_CS_IOS				0x00000001		/*IO SPACE */


#define QBSI0_CTL_PAS			0X01000000
#define	QBSI0_CTL_PWEN			0X80000000
#define	QBSI0_CTL_PREN			0X08000000
#define	QBSI0_AT_EN				0X00000001
#define	QBSI0_AT_BS				0X00000080		/*2M  block size*/
#define	QBSI0_AT_TA				0X80000000

#define QSPAN_QBSI0_PWEN		0x80000000

#define QSPAN_IDMA_WRITE 	0x01
#define QSPAN_IDMA_READ  	0x02

#define QSPAN_BASE_ADRS 	CPU_PCI_BRIDGE_BA
#define CT69K_BASE_ADRS		CPU_PCI_CT69000_BA
#define PCI_MSTR_IO_LOCAL 	0

#define QSPAN_PCI_CHNL0 	0
#define QSPAN_PCI_CHNL1		1

#define PCI_CS_MS				0x00000002		/*MEMORY SPACE*/
#define PCI_CS_IOS				0x00000001		/*IO SPACE */

#define CON_ADD_BUS		0x00FF0000	/* Bus Number */
#define CON_ADD_DEV		0x00007800	/* Device Number */
#define CON_ADD_FUNC	0x00000700	/* Function Number */
#define CON_ADD_REG		0x000000FC	/* Register Number */
#define CON_ADD_TYPE	0x00000001	/* Configuration Cycle Type */
#define CON_ADD_RESRV	0xFF008002	/* Reserved Bits */

/*
 * QBus Slave Image X Address Translation Register
 */
#define QBSI_AT_TA			0xFFFF0000	/* Translation Address */
#define QBSI_AT_BS			0x000000F0	/* Block Size */
#define QBSI_AT_EN			0x00000001	/* Enable Address Translation */
#define QBSI_AT_RESRVD	0x0000FF0E	/* Reserved Bits */


#define PCI_DEVICE_NUM	1

typedef struct qspan {
	VUINT32  pci_id;		/* PCI Configuration Space ID Reg */
	VUINT32  pci_cs;		/* PCI Configuration CS Reg */
	VUINT32  pci_class;		/* PCI Configuration Class Reg */
	VUINT32  pci_misc0;		/* PCI Configuration Misc 0 Reg*/
	VUINT32  pci_bsm;		/* PCI Configuration BA for Regs */
  	UINT8 RESERVED1[0x4];
	VUINT32  pci_bst0;		/* PCI Configuration BA for TI0 */
	VUINT32  pci_bst1;		/* PCI Configuration BA for TI1 */
	UINT8 RESERVED2[0xC];
	VUINT32  pci_sid;		/* PCI Configuration Subsystem ID */
	VUINT32  pci_bsrom;		/* PCI Configuration ExpROM BA */
  	VUINT32  pci_cp;    	/* 2.0+ PCI Capabilities Pointer Register */
  	UINT8 RESERVED3[0x4];
	VUINT32  pci_misc1;		/* PCI Configuration Misc 1 Reg */
  	UINT8 RESERVED4[0x9C];
  	VUINT32  pci_pmc;   	/* 2.0+ PCI Power Management Capabilities Reg */
  	VUINT32  pci_pmcs;  	/* 2.0+ PCI Power Management CS Reg*/
  	VUINT32  cpci_hs;   	/* 2.0+ Compact PCI Hot Swap Register */
	VUINT32  pci_vpd;   	/* 2.0+ PCI Vital Product Data (VPD) Register */
  	VUINT32  vpd_data;  	/* 2.0+ PCI VPD Data Register */
  	UINT8 RESERVED5[0x10];
	VUINT32  pbti0_ctl;		/* PCI Bus Target Image 0 Control Reg */
	VUINT32  pbti0_add;		/* PCI Bus Target Image 0 Address Reg */
  	UINT8 RESERVED6[0x8];
	VUINT32  pbti1_ctl;		/* PCI Bus Target Image 1 Control Reg */
	VUINT32  pbti1_add;		/* PCI Bus Target Image 1 Address Reg */
  	UINT8 RESERVED7[0x24];
	VUINT32  pbrom_ctl;		/* PCI Bus Exp Rom Control Reg  */
	VUINT32  pb_errcs;		/* PCI Bus Error CSR */
	VUINT32  pb_aerr;		/* PCI Bus Address Error Log Reg */
	VUINT32  pb_derr;		/* PCI Bus Data Error Log Reg */
  	UINT8 RESERVED8[0xB4];
  	VUINT32  i2o_cs;    	/* 2.0+ I2O Control and Status Register */
  	VUINT32  iif_tp;    	/* 2.0+ I2O Inbound Free_List Top Pointer Reg */
  	VUINT32  iif_bp;    	/* 2.0+ I2O Inbound Free_List Bottom Pointer Reg */
  	VUINT32  iip_tp;    	/* 2.0+ I2O Inbound Post_List Top Pointer Reg */
  	VUINT32  iip_bp;    	/* 2.0+ I2O Inbound Post_List Bottom Pointer Reg */
  	VUINT32  iof_tp;    	/* 2.0+ I2O Outbound Free_List Top Pointer Reg */
  	VUINT32  iof_bp;    	/* 2.0+ I2O Outbound Free_List Bottom Pointer Reg */
  	VUINT32  iop_tp;    	/* 2.0+ I2O Outbound Post_List Top Pointer Reg */
  	VUINT32  iop_bp;    	/* 2.0+ I2O Outbound Post_List Bottom Pointer Reg */
  	UINT8 RESERVED9[0x1DC];
	VUINT32  idma_cs;		/* IDMA Control and Status Reg */
	VUINT32  idma_add;		/* IDMA Address Reg */
	VUINT32  idma_cnt;		/* IDMA Transfer Count Reg */
  	VUINT32  dma_qadd;  	/* 2.0+ DMA QBus Address Register */
  	VUINT32  dma_cs;    	/* 2.0+ DMA Control and Status Register */
  	VUINT32  dma_cpp;   	/* 2.0+ DMA Command Packet Pointer Register */
  	UINT8 RESERVED10[0xE8];
	VUINT32  con_add;		/* PCI Configuration Cycle Addr Reg */
	VUINT32  con_data;		/* PCI Configuration Cycle Data Reg */
	VUINT32  iack_gen;		/* IACK Cycle Generation Reg */
  	UINT8 RESERVED11[0xF4];
	VUINT32  int_stat;		/* Interrupt Status Reg */
	VUINT32  int_ctl;		/* Interrupt Control Reg */
	VUINT32  int_dir;		/* Interrupt Direction Control Reg */
	VUINT32  int_ctl2;		/* 1.2+ Interrupt Control 2 Reg */
  	UINT8 RESERVED12[0xF0];
  	VUINT32  mbox0;     	/* 2.0+ Mailbox Register 0 */
  	VUINT32  mbox1;     	/* 2.0+ Mailbox Register 1 */
  	VUINT32  mbox2;     	/* 2.0+ Mailbox Register 2 */
  	VUINT32  mbox3;     	/* 2.0+ Mailbox Register 3 */
  	UINT8 RESERVED13[0xF0];
	VUINT32  misc_ctl;		/* Misc Control and Status Reg */
	VUINT32  eeprom_cs;		/* EEPROM Control and Status Reg */
	VUINT32  misc_ctl2;		/* 2.0+ Misc Control 2 Register */
  	UINT8 RESERVED14[0x6F4];
	VUINT32  qbsi0_ctl;		/* QBus Slave Image 0 Control Reg */
	VUINT32  qbsi0_at;		/* QBus SI0 Address Translation Reg */
  	UINT8 RESERVED15[0x8];
	VUINT32  qbsi1_ctl;		/* QBus Slave Image 1 Control Reg */
	VUINT32  qbsi1_at;		/* QBus SI1 Address Translation Reg */
  	UINT8 RESERVED16[0x68];
	VUINT32  qb_errcs;		/* QBus Error Log CSR  */
	VUINT32  qb_aerr;		/* QBus Address Error Log Reg */
	VUINT32  qb_derr;		/* QBus Data Error Log Reg */
  	UINT8 RESERVED17[0x74];
} QSPAN, *PQSPAN;



void SysQspanHwInit(PQSPAN qspanAdr);
void qspanHostReset
    (
    PQSPAN qspanAdr        	/* base address of the QSpan device regs. */
    );
void qspanHostEnable
    (
    PQSPAN      qspanAdr  	/* base address of the QSpan device regs. */
    );
void qspanSpaceAccesses
	(
	PQSPAN 	qspanAdr,		/* base address of the QSpan device regs. */
	UINT8 	status			/* assign the memory or IO space*/
	);
void qspanBurstConfigure
	(
	PQSPAN qspanAdr,		/* base address of the QSpan device regs. */
	UINT8 	image,			/* assign the image0 or image1*/
	UINT8	status			/* assign enable or disable*/
	);
void sysPCISpaceAssign();
UINT32 qspanPciConfigurationRead(
	PQSPAN qspan,
	UINT32 cycle_type,
	UINT32 bus_num,
	UINT32 dev_num,
	UINT32 func_num,
	UINT32 reg_num
	);
void qspanIOControl
	(
	PQSPAN qspanAdr,
	UINT32 status
	);




#ifdef __cplusplus
}
#endif

#endif