53c7,8xx.h

GNU Mach 微内核源代码, 基于美国卡内基美隆大学的 Mach 研究项目

#define DMODE_REG_00		0x34 	/* DMA mode rw */
#define DMODE_00_BL1	0x80	/* Burst length bits */
#define DMODE_00_BL0	0x40
#define DMODE_BL_MASK	0xc0
/* Burst lengths (800) */
#define DMODE_BL_2	0x00	/* 2 transfer */
#define DMODE_BL_4	0x40	/* 4 transfers */
#define DMODE_BL_8	0x80	/* 8 transfers */
#define DMODE_BL_16	0xc0	/* 16 transfers */

#define DMODE_700_BW16	0x20	/* Host buswidth = 16 */
#define DMODE_700_286	0x10	/* 286 mode */
#define DMODE_700_IOM	0x08	/* Transfer to IO port */
#define DMODE_700_FAM	0x04	/* Fixed address mode */
#define DMODE_700_PIPE	0x02	/* Pipeline mode disables 
					 * automatic fetch / exec 
					 */
#define DMODE_MAN	0x01		/* Manual start mode, 
					 * requires a 1 to be written
					 * to the start DMA bit in the DCNTL
					 * register to run scripts 
					 */

#define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )

/* NCR53c800 series only */
#define SCRATCHA_REG_800	0x34	/* through 0x37 Scratch A rw */
/* NCR53c710 only */
#define SCRATCB_REG_10		0x34	/* through 0x37 scratch B rw */

#define DMODE_REG_10    	0x38	/* DMA mode rw, NCR53c710 and newer */
#define DMODE_800_SIOM		0x20	/* Source IO = 1 */
#define DMODE_800_DIOM		0x10	/* Destination IO = 1 */
#define DMODE_800_ERL		0x08	/* Enable Read Line */

/* 35-38 are reserved on 700 and 700-66 series chips */
#define DIEN_REG		0x39	/* DMA interrupt enable rw */
/* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
#define DIEN_800_MDPE		0x40	/* Master data parity error */
#define DIEN_800_BF		0x20	/* BUS fault */
#define DIEN_ABRT		0x10	/* Enable aborted interrupt */
#define DIEN_SSI		0x08	/* Enable single step interrupt */
#define DIEN_SIR		0x04	/* Enable SCRIPTS INT command 
					 * interrupt
					 */
/* 0x02 is reserved on 800 series chips */
#define DIEN_700_WTD		0x02	/* Enable watchdog timeout interrupt */
#define DIEN_700_OPC		0x01	/* Enable illegal instruction 
					 * interrupt 
					 */
#define DIEN_800_IID		0x01	/*  Same meaning, different name */ 

/*
 * DMA watchdog timer rw
 * set in 16 CLK input periods.
 */
#define DWT_REG			0x3a

/* DMA control rw */
#define DCNTL_REG		0x3b
#define DCNTL_700_CF1		0x80	/* Clock divisor bits */
#define DCNTL_700_CF0		0x40
#define DCNTL_700_CF_MASK	0xc0
/* Clock divisors 			   Divisor SCLK range (MHZ) */
#define DCNTL_700_CF_2		0x00    /* 2.0	   37.51-50.00 */
#define DCNTL_700_CF_1_5	0x40	/* 1.5	   25.01-37.50 */
#define DCNTL_700_CF_1		0x80	/* 1.0     16.67-25.00 */
#define DCNTL_700_CF_3		0xc0	/* 3.0	   50.01-66.67 (53c700-66) */

#define DCNTL_700_S16		0x20	/* Load scripts 16 bits at a time */
#define DCNTL_SSM		0x10	/* Single step mode */
#define DCNTL_700_LLM		0x08	/* Low level mode, can only be set 
					 * after selection */
#define DCNTL_800_IRQM		0x08	/* Totem pole IRQ pin */
#define DCNTL_STD		0x04	/* Start DMA / SCRIPTS */
/* 0x02 is reserved */
#define DCNTL_00_RST		0x01	/* Software reset, resets everything
					 * but 286 mode bit  in DMODE. On the
					 * NCR53c710, this bit moved to CTEST8
					 */
#define DCNTL_10_COM		0x01	/* 700 software compatibility mode */

#define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)


/* NCR53c700-66 only */
#define SCRATCHB_REG_00		0x3c	/* through 0x3f scratch b rw */
#define SCRATCHB_REG_800	0x5c	/* through 0x5f scratch b rw */
/* NCR53c710 only */
#define ADDER_REG_10		0x3c	/* Adder, NCR53c710 only */

#define SIEN1_REG_800		0x41
#define SIEN1_800_STO		0x04	/* selection/reselection timeout */
#define SIEN1_800_GEN		0x02	/* general purpose timer */
#define SIEN1_800_HTH		0x01	/* handshake to handshake */

#define SIST1_REG_800		0x43
#define SIST1_800_STO		0x04	/* selection/reselection timeout */
#define SIST1_800_GEN		0x02	/* general purpose timer */
#define SIST1_800_HTH		0x01	/* handshake to handshake */

#define SLPAR_REG_800		0x44	/* Parity */

#define MACNTL_REG_800		0x46	/* Memory access control */
#define MACNTL_800_TYP3		0x80
#define MACNTL_800_TYP2		0x40
#define MACNTL_800_TYP1		0x20
#define MACNTL_800_TYP0		0x10
#define MACNTL_800_DWR		0x08
#define MACNTL_800_DRD		0x04
#define MACNTL_800_PSCPT	0x02
#define MACNTL_800_SCPTS	0x01

#define GPCNTL_REG_800		0x47	/* General Purpose Pin Control */

/* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
#define STIME0_REG_800		0x48	/* SCSI Timer Register 0 */
#define STIME0_800_HTH_MASK	0xf0	/* Handshake to Handshake timeout */
#define STIME0_800_HTH_SHIFT	4
#define STIME0_800_SEL_MASK	0x0f	/* Selection timeout */
#define STIME0_800_SEL_SHIFT	0

#define STIME1_REG_800		0x49
#define STIME1_800_GEN_MASK	0x0f	/* General purpose timer */

#define RESPID_REG_800		0x4a	/* Response ID, bit fielded.  8
					   bits on narrow chips, 16 on WIDE */

#define STEST0_REG_800		0x4c	
#define STEST0_800_SLT		0x08	/* Selection response logic test */
#define STEST0_800_ART		0x04	/* Arbitration priority encoder test */
#define STEST0_800_SOZ		0x02	/* Synchronous offset zero */
#define STEST0_800_SOM		0x01	/* Synchronous offset maximum */

#define STEST1_REG_800		0x4d
#define STEST1_800_SCLK		0x80	/* Disable SCSI clock */

#define STEST2_REG_800		0x4e	
#define STEST2_800_SCE		0x80	/* Enable SOCL/SODL */
#define STEST2_800_ROF		0x40	/* Reset SCSI sync offset */
#define STEST2_800_SLB		0x10	/* Enable SCSI loopback mode */
#define STEST2_800_SZM		0x08	/* SCSI high impedance mode */
#define STEST2_800_EXT		0x02	/* Extend REQ/ACK filter 30 to 60ns */
#define STEST2_800_LOW		0x01	/* SCSI low level mode */

#define STEST3_REG_800		0x4f	 
#define STEST3_800_TE		0x80	/* Enable active negation */
#define STEST3_800_STR		0x40	/* SCSI FIFO test read */
#define STEST3_800_HSC		0x20	/* Halt SCSI clock */
#define STEST3_800_DSI		0x10	/* Disable single initiator response */
#define STEST3_800_TTM		0x04	/* Time test mode */
#define STEST3_800_CSF		0x02	/* Clear SCSI FIFO */
#define STEST3_800_STW		0x01	/* SCSI FIFO test write */

#define OPTION_PARITY 		0x1	/* Enable parity checking */
#define OPTION_TAGGED_QUEUE	0x2	/* Enable SCSI-II tagged queuing */
#define OPTION_700		0x8	/* Always run NCR53c700 scripts */
#define OPTION_INTFLY		0x10	/* Use INTFLY interrupts */
#define OPTION_DEBUG_INTR	0x20	/* Debug interrupts */
#define OPTION_DEBUG_INIT_ONLY	0x40	/* Run initialization code and 
					   simple test code, return
					   DID_NO_CONNECT if any SCSI
					   commands are attempted. */
#define OPTION_DEBUG_READ_ONLY	0x80	/* Return DID_ERROR if any 
					   SCSI write is attempted */
#define OPTION_DEBUG_TRACE	0x100	/* Animated trace mode, print 
					   each address and instruction 
					   executed to debug buffer. */
#define OPTION_DEBUG_SINGLE	0x200	/* stop after executing one 
					   instruction */
#define OPTION_SYNCHRONOUS	0x400	/* Enable sync SCSI.  */
#define OPTION_MEMORY_MAPPED	0x800	/* NCR registers have valid 
					   memory mapping */
#define OPTION_IO_MAPPED	0x1000  /* NCR registers have valid
					     I/O mapping */
#define OPTION_DEBUG_PROBE_ONLY	0x2000  /* Probe only, don't even init */
#define OPTION_DEBUG_TESTS_ONLY	0x4000  /* Probe, init, run selected tests */
#define OPTION_DEBUG_TEST0	0x08000 /* Run test 0 */
#define OPTION_DEBUG_TEST1	0x10000 /* Run test 1 */
#define OPTION_DEBUG_TEST2	0x20000 /* Run test 2 */
#define OPTION_DEBUG_DUMP	0x40000 /* Dump commands */
#define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
#define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
#define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
#define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
#define OPTION_DEBUG_DSA 0x800000
#define OPTION_DEBUG_CORRUPTION	0x1000000	/* Detect script corruption */
#define OPTION_DEBUG_SDTR       0x2000000	/* Debug SDTR problem */
#define OPTION_DEBUG_MISMATCH 	0x4000000 	/* Debug phase mismatches */
#define OPTION_DISCONNECT	0x8000000	/* Allow disconnect */
#define OPTION_DEBUG_DISCONNECT 0x10000000	
#define OPTION_ALWAYS_SYNCHRONOUS 0x20000000	/* Negotiate sync. transfers
						   on power up */
#define OPTION_DEBUG_QUEUES	0x80000000	
#define OPTION_DEBUG_ALLOCATION 0x100000000LL
#define OPTION_DEBUG_SYNCHRONOUS 0x200000000LL	/* Sanity check SXFER and 
						   SCNTL3 registers */
#define OPTION_NO_ASYNC	0x400000000LL		/* Don't automagically send
						   SDTR for async transfers when
						   we haven't been told to do
						   a synchronous transfer. */
#define OPTION_NO_PRINT_RACE 0x800000000LL	/* Don't print message when
						   the reselect/WAIT DISCONNECT
						   race condition hits */
#if !defined(PERM_OPTIONS)
#define PERM_OPTIONS 0
#endif
				
struct NCR53c7x0_synchronous {
    u32 select_indirect;		/* Value used for indirect selection */
    u32 script[8];			/* Size ?? Script used when target is 
						reselected */
    unsigned char synchronous_want[5];	/* Per target desired SDTR */
/* 
 * Set_synchronous programs these, select_indirect and current settings after
 * int_debug_should show a match.
 */
    unsigned char sxfer_sanity, scntl3_sanity;
};

#define CMD_FLAG_SDTR 		1	/* Initiating synchronous 
					   transfer negotiation */
#define CMD_FLAG_WDTR		2	/* Initiating wide transfer
					   negotiation */
#define CMD_FLAG_DID_SDTR	4	/* did SDTR */
#define CMD_FLAG_DID_WDTR	8	/* did WDTR */

struct NCR53c7x0_table_indirect {
    u32 count;
    void *address;
};

enum ncr_event { 
    EVENT_NONE = 0,
/* 
 * Order is IMPORTANT, since these must correspond to the event interrupts
 * in 53c7,8xx.scr 
 */

    EVENT_ISSUE_QUEUE = 0x5000000,	/* Command was added to issue queue */
    EVENT_START_QUEUE,			/* Command moved to start queue */
    EVENT_SELECT,			/* Command completed selection */
    EVENT_DISCONNECT,			/* Command disconnected */
    EVENT_RESELECT,			/* Command reselected */
    EVENT_COMPLETE,		        /* Command completed */
    EVENT_IDLE,
    EVENT_SELECT_FAILED,
    EVENT_BEFORE_SELECT,
    EVENT_RESELECT_FAILED
};

struct NCR53c7x0_event {
    enum ncr_event event;	/* What type of event */
    unsigned char target;
    unsigned char lun;
    struct timeval time;	
    u32 *dsa;			/* What's in the DSA register now (virt) */
/* 
 * A few things from that SCSI pid so we know what happened after 
 * the Scsi_Cmnd structure in question may have disappeared.
 */
    unsigned long pid;		/* The SCSI PID which caused this 
				   event */
    unsigned char cmnd[12];
};

/*
 * Things in the NCR53c7x0_cmd structure are split into two parts :
 *
 * 1.  A fixed portion, for things which are not accessed directly by static NCR
 *	code (ie, are referenced only by the Linux side of the driver,
 *	or only by dynamically generated code).  
 *
 * 2.  The DSA portion, for things which are accessed directly by static NCR
 *	code.
 *
 * This is a little ugly, but it 
 * 1.  Avoids conflicts between the NCR code's picture of the structure, and 
 * 	Linux code's idea of what it looks like.
 *
 * 2.  Minimizes the pain in the Linux side of the code needed 
 * 	to calculate real dsa locations for things, etc.
 * 
 */

struct NCR53c7x0_cmd {
    void *real;				/* Real, unaligned address for
					   free function */
    void (* free)(void *, int);		/* Command to deallocate; NULL
					   for structures allocated with
					   scsi_register, etc. */
    Scsi_Cmnd *cmd;			/* Associated Scsi_Cmnd 
					   structure, Scsi_Cmnd points
					   at NCR53c7x0_cmd using 
					   host_scribble structure */

    int size;				/* scsi_malloc'd size of this 
					   structure */

    int flags;				/* CMD_* flags */

/*
 * SDTR and WIDE messages are an either/or affair
 * in this message, since we will go into message out and send
 * _the whole mess_ without dropping out of message out to 
 * let the target go into message in after sending the first 
 * message.
 */

    unsigned char select[11];		/* Select message, includes
					   IDENTIFY
					   (optional) QUEUE TAG
 				 	   (optional) SDTR or WDTR
					 */


    volatile struct NCR53c7x0_cmd *next; /* Linux maintained lists (free,
					    running, eventually finished */
    					 

    u32 *data_transfer_start;		/* Start of data transfer routines */
    u32 *data_transfer_end;		/* Address after end of data transfer o
    	    	    	    	    	   routines */
/* 
 * The following three fields were moved from the DSA proper to here
 * since only dynamically generated NCR code refers to them, meaning
 * we don't need dsa_* absolutes, and it is simpler to let the 
 * host code refer to them directly.
 */

/* 
 * HARD CODED : residual and saved_residual need to agree with the sizes
 * used in NCR53c7,8xx.scr.  
 * 
 * FIXME: we want to consider the case where we have odd-length 
 *	scatter/gather buffers and a WIDE transfer, in which case 
 *	we'll need to use the CHAIN MOVE instruction.  Ick.
 */
    u32 residual[6];			/* Residual data transfer which
					   allows pointer code to work
					   right.

    	    	    	    	    	    [0-1] : Conditional call to 
    	    	    	    	    	    	appropriate other transfer 
    	    	    	    	    	    	routine.
    	    	    	    	    	    [2-3] : Residual block transfer
    	    	    	    	    	    	instruction.
    	    	    	    	    	    [4-5] : Jump to instruction
    	    	    	    	    	    	after splice.
					 */
    u32 saved_residual[6]; 		/* Copy of old residual, so we 
					   can get another partial 
					   transfer and still recover 
    	    	    	    	    	 */
    	    	
    u32 saved_data_pointer;		/* Saved data pointer */

    u32 dsa_next_addr;		        /* _Address_ of dsa_next field  
					   in this dsa for RISCy 
					   style constant. */

    u32 dsa_addr;			/* Address of dsa; RISCy style
					   constant */

    u32 dsa[0];				/* Variable length (depending
					   on host type, number of scatter /
					   gather buffers, etc).  */
};

struct NCR53c7x0_break {
    u32 *address, old_instruction[2];
    struct NCR53c7x0_break *next;
    unsigned char old_size;		/* Size of old instruction */
};

/* Indicates that the NCR is not executing code */
#define STATE_HALTED	0		
/* 
 * Indicates that the NCR is executing the wait for select / reselect 
 * script.  Only used when running NCR53c700 compatible scripts, only 
 * state during which an ABORT is _not_ considered an error condition.
 */
#define STATE_WAITING	1		
/* Indicates that the NCR is executing other code. */
#define STATE_RUNNING	2		
/* 
 * Indicates that the NCR was being aborted.
 */
#define STATE_ABORTING	3
/* Indicates that the NCR was successfully aborted. */
#define STATE_ABORTED 4
/* Indicates that the NCR has been disabled due to a fatal error */
#define STATE_DISABLED 5

/* 
 * Where knowledge of SCSI SCRIPT(tm) specified values are needed 
 * in an interrupt handler, an interrupt handler exists for each