📄 scripts.h

📁 GNU Mach 微内核源代码, 基于美国卡内基美隆大学的 Mach 研究项目
💻 H
📖 第 1 页 / 共 3 页
字号:
	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseB+  112,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseB+   120,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseB+  120,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseB+   128,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0   /* offset dout_phaseB+  128 */	};ULONG  jump_table0[]={	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_	};ULONG  jmp_din_pad_0[]={	0,	/* offset din_pad_0,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_	};ULONG  jmp_dout_pad_0[]={	0	/* offset dout_pad_0 */	};#define jump_tableB	jump_table0/*;==========================================================; Data in phase;==========================================================*/ULONG  din_phaseB[]={	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment0,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment1,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment2,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment3,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment4,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment5,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment6,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment7,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment8,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment9,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment10,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment11,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment12,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment13,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment14,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment15,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment0,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment1,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment2,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment3,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment4,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment5,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment6,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment7,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment8,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment9,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment10,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment11,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment12,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment13,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment14,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment15,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_,	0, /* offset SRB.Segment16,*/	RD_MODIFY_WRT+OP_OR+0x100+0x340000, /*;(1 shl 8) or (__scratcha shl 16)*/	0,	DCMD_JUMP+WAIT_PHASE_VALID+IF_NOT+PHASE_CMP+DATA_IN_	};ULONG  jmp_status1_phase[]={	0	/* offset status1_phase */	};#define din_phase	din_phaseBULONG  din_pad_0[]={	RD_MODIFY_WRT+OP_OR+0x340000+0x400,  /*;(4 shl 8) or (__scratcha shl 16)*/	0	};ULONG  din_pad_addrB[]={	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_IN_	};ULONG  SRB_SegmentPad[]={	0,	/* offset SRB.SegmentPad,*/	DCMD_JUMP+IF_TRUE	};ULONG  jmp_din_pad_addrB[]={	0	/* offset din_pad_addrB */	};/*;==========================================================; Data out phase;==========================================================*/ULONG  dout_phaseB[]={	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment0,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment1,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment2,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment3,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment4,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment5,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment6,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment7,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment8,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment9,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment10,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment11,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment12,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment13,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment14,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment15,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment0,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment1,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment2,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment3,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment4,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment5,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment6,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment7,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment8,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment9,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment10,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment11,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment12,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment13,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment14,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment15,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_,	0, /* offset SRB.Segment16,*/	RD_MODIFY_WRT+OP_OR+0x100+0x340000, /*;(1 shl 8) or (__scratcha shl 16)*/	0,	DCMD_JUMP+WAIT_PHASE_VALID+IF_NOT+PHASE_CMP+DATA_OUT_	};ULONG  jmp_status1_phase1[]={	0	/* offset status1_phase */	};#define dout_phase	dout_phaseBULONG  dout_pad_0[]={	RD_MODIFY_WRT+OP_OR+0x340000+0x400, /*;(4 shl 8) or (__scratcha shl 16)*/	0	};ULONG  dout_pad_addrB[]={	DCMD_BLOCK_MOVE+TABLE_INDIRECT+BLOCK_MOVE+DATA_OUT_	};ULONG  SRB_SegmentPad1[]={	0,	/* offset SRB.SegmentPad,*/	DCMD_JUMP+IF_TRUE	};ULONG  jmp_dout_pad_addrB[]={	0	/* offset dout_pad_addrB */	};/*;==========================================================; Data phase jump table for WIDE SCSI operation;==========================================================*/ULONG  jmp_dio_phaseW[]={	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+   0,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+  0,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+   8,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+  8,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  16,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 16,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  24,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 24,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  32,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 32,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  40,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 40,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  48,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 48,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  56,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 56,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  64,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 64,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  72,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 72,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  80,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 80,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  88,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 88,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  96,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 96,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  104,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 104,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  112,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 112,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  120,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 120,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+   0,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+  0,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+   8,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+  8,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  16,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 16,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  24,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 24,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  32,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 32,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  40,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 40,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  48,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 48,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  56,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 56,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  64,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 64,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  72,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 72,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  80,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 80,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  88,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 88,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  96,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 96,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  104,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 104,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  112,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 112,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  120,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0,  /* offset dout_phaseW+ 120,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_,	0,  /* offset din_phaseW+  128,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_,	0   /* offset dout_phaseW+ 128 */	};ULONG  jump_tablew[]={	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_IN_	};ULONG  jmp_din_pad_1[]={	0,	/* offset din_pad_1,*/	DCMD_JUMP+WAIT_PHASE_VALID+IF_TRUE+PHASE_CMP+DATA_OUT_	};ULONG  jmp_dout_pad_1[]={	0	/* offset dout_pad_1 */	};#define jump_tableW	jump_tablew/*;==========================================================; Data in phase;==========================================================*/ULONG  din_phaseW[]={	DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,	0, /* offset SRB.Segment0,*/	DCMD_BLOCK_MOVE+TABLE_INDIRECT+CHAIN_MOVE+DATA_IN_,
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -