tmscsim.h

GNU Mach 微内核源代码, 基于美国卡内基美隆大学的 Mach 研究项目

#define SYNC_NEGO_OFFSET 15

/*;---SCSI bus phase*/
#define SCSI_DATA_OUT	0
#define SCSI_DATA_IN	1
#define SCSI_COMMAND	2
#define SCSI_STATUS_	3
#define SCSI_NOP0	4
#define SCSI_NOP1	5
#define SCSI_MSG_OUT	6
#define SCSI_MSG_IN	7

/*;----SCSI MSG BYTE*/
#define MSG_COMPLETE		0x00
#define MSG_EXTENDED		0x01
#define MSG_SAVE_PTR		0x02
#define MSG_RESTORE_PTR 	0x03
#define MSG_DISCONNECT		0x04
#define MSG_INITIATOR_ERROR	0x05
#define MSG_ABORT		0x06
#define MSG_REJECT_		0x07
#define MSG_NOP 		0x08
#define MSG_PARITY_ERROR	0x09
#define MSG_LINK_CMD_COMPL	0x0A
#define MSG_LINK_CMD_COMPL_FLG	0x0B
#define MSG_BUS_RESET		0x0C
#define MSG_ABORT_TAG		0x0D
#define MSG_SIMPLE_QTAG 	0x20
#define MSG_HEAD_QTAG		0x21
#define MSG_ORDER_QTAG		0x22
#define MSG_IDENTIFY		0x80
#define MSG_HOST_ID		0x0C0

/*;----SCSI STATUS BYTE*/
#define STATUS_GOOD		0x00
#define CHECK_CONDITION_	0x02
#define STATUS_BUSY		0x08
#define STATUS_INTERMEDIATE	0x10
#define RESERVE_CONFLICT	0x18

/* cmd->result */
#define STATUS_MASK_		0xFF
#define MSG_MASK		0xFF00
#define RETURN_MASK		0xFF0000

/*
**  Inquiry Data format
*/

typedef struct	_SCSIInqData { /* INQ */

	UCHAR	 DevType;		/* Periph Qualifier & Periph Dev Type*/
	UCHAR	 RMB_TypeMod;		/* rem media bit & Dev Type Modifier */
	UCHAR	 Vers;			/* ISO, ECMA, & ANSI versions	     */
	UCHAR	 RDF;			/* AEN, TRMIOP, & response data format*/
	UCHAR	 AddLen;		/* length of additional data	     */
	UCHAR	 Res1;			/* reserved			     */
	UCHAR	 Res2;			/* reserved			     */
	UCHAR	 Flags; 		/* RelADr,Wbus32,Wbus16,Sync,etc.    */
	UCHAR	 VendorID[8];		/* Vendor Identification	     */
	UCHAR	 ProductID[16]; 	/* Product Identification	     */
	UCHAR	 ProductRev[4]; 	/* Product Revision		     */


} SCSI_INQDATA, *PSCSI_INQDATA;


/*  Inquiry byte 0 masks */


#define SCSI_DEVTYPE	    0x1F      /* Peripheral Device Type 	    */
#define SCSI_PERIPHQUAL     0xE0      /* Peripheral Qualifier		    */


/*  Inquiry byte 1 mask */

#define SCSI_REMOVABLE_MEDIA  0x80    /* Removable Media bit (1=removable)  */


/*  Peripheral Device Type definitions */

#define SCSI_DASD		 0x00	   /* Direct-access Device	   */
#define SCSI_SEQACESS		 0x01	   /* Sequential-access device	   */
#define SCSI_PRINTER		 0x02	   /* Printer device		   */
#define SCSI_PROCESSOR		 0x03	   /* Processor device		   */
#define SCSI_WRITEONCE		 0x04	   /* Write-once device 	   */
#define SCSI_CDROM		 0x05	   /* CD-ROM device		   */
#define SCSI_SCANNER		 0x06	   /* Scanner device		   */
#define SCSI_OPTICAL		 0x07	   /* Optical memory device	   */
#define SCSI_MEDCHGR		 0x08	   /* Medium changer device	   */
#define SCSI_COMM		 0x09	   /* Communications device	   */
#define SCSI_NODEV		 0x1F	   /* Unknown or no device type    */

/*
** Inquiry flag definitions (Inq data byte 7)
*/

#define SCSI_INQ_RELADR       0x80    /* device supports relative addressing*/
#define SCSI_INQ_WBUS32       0x40    /* device supports 32 bit data xfers  */
#define SCSI_INQ_WBUS16       0x20    /* device supports 16 bit data xfers  */
#define SCSI_INQ_SYNC	      0x10    /* device supports synchronous xfer   */
#define SCSI_INQ_LINKED       0x08    /* device supports linked commands    */
#define SCSI_INQ_CMDQUEUE     0x02    /* device supports command queueing   */
#define SCSI_INQ_SFTRE	      0x01    /* device supports soft resets */


/*
;==========================================================
; EEPROM byte offset
;==========================================================
*/
typedef  struct  _EEprom
{
UCHAR	EE_MODE1;
UCHAR	EE_SPEED;
UCHAR	xx1;
UCHAR	xx2;
} EEprom, *PEEprom;

#define EE_ADAPT_SCSI_ID 64
#define EE_MODE2	65
#define EE_DELAY	66
#define EE_TAG_CMD_NUM	67

/*; EE_MODE1 bits definition*/
#define PARITY_CHK_	BIT0
#define SYNC_NEGO_	BIT1
#define EN_DISCONNECT_	BIT2
#define SEND_START_	BIT3
#define TAG_QUEUING_	BIT4

/*; EE_MODE2 bits definition*/
#define MORE2_DRV	BIT0
#define GREATER_1G	BIT1
#define RST_SCSI_BUS	BIT2
#define ACTIVE_NEGATION BIT3
#define NO_SEEK 	BIT4
#define LUN_CHECK	BIT5

#define ENABLE_CE	1
#define DISABLE_CE	0
#define EEPROM_READ	0x80

/*
;==========================================================
;	AMD 53C974 Registers bit Definition
;==========================================================
*/
/*
;====================
; SCSI Register
;====================
*/

/*; Command Reg.(+0CH) */
#define DMA_COMMAND		BIT7
#define NOP_CMD 		0
#define CLEAR_FIFO_CMD		1
#define RST_DEVICE_CMD		2
#define RST_SCSI_BUS_CMD	3
#define INFO_XFER_CMD		0x10
#define INITIATOR_CMD_CMPLTE	0x11
#define MSG_ACCEPTED_CMD	0x12
#define XFER_PAD_BYTE		0x18
#define SET_ATN_CMD		0x1A
#define RESET_ATN_CMD		0x1B
#define SELECT_W_ATN		0x42
#define SEL_W_ATN_STOP		0x43
#define EN_SEL_RESEL		0x44
#define SEL_W_ATN2		0x46
#define DATA_XFER_CMD		INFO_XFER_CMD


/*; SCSI Status Reg.(+10H) */
#define INTERRUPT		BIT7
#define ILLEGAL_OP_ERR		BIT6
#define PARITY_ERR		BIT5
#define COUNT_2_ZERO		BIT4
#define GROUP_CODE_VALID	BIT3
#define SCSI_PHASE_MASK 	(BIT2+BIT1+BIT0)

/*; Interrupt Status Reg.(+14H) */
#define SCSI_RESET		BIT7
#define INVALID_CMD		BIT6
#define DISCONNECTED		BIT5
#define SERVICE_REQUEST 	BIT4
#define SUCCESSFUL_OP		BIT3
#define RESELECTED		BIT2
#define SEL_ATTENTION		BIT1
#define SELECTED		BIT0

/*; Internal State Reg.(+18H) */
#define SYNC_OFFSET_FLAG	BIT3
#define INTRN_STATE_MASK	(BIT2+BIT1+BIT0)

/*; Clock Factor Reg.(+24H) */
#define CLK_FREQ_40MHZ		0
#define CLK_FREQ_35MHZ		(BIT2+BIT1+BIT0)
#define CLK_FREQ_30MHZ		(BIT2+BIT1)
#define CLK_FREQ_25MHZ		(BIT2+BIT0)
#define CLK_FREQ_20MHZ		BIT2
#define CLK_FREQ_15MHZ		(BIT1+BIT0)
#define CLK_FREQ_10MHZ		BIT1

/*; Control Reg. 1(+20H) */
#define EXTENDED_TIMING 	BIT7
#define DIS_INT_ON_SCSI_RST	BIT6
#define PARITY_ERR_REPO 	BIT4
#define SCSI_ID_ON_BUS		(BIT2+BIT1+BIT0)

/*; Control Reg. 2(+2CH) */
#define EN_FEATURE		BIT6
#define EN_SCSI2_CMD		BIT3

/*; Control Reg. 3(+30H) */
#define ID_MSG_CHECK		BIT7
#define EN_QTAG_MSG		BIT6
#define EN_GRP2_CMD		BIT5
#define FAST_SCSI		BIT4	/* ;10MB/SEC */
#define FAST_CLK		BIT3	/* ;25 - 40 MHZ */

/*; Control Reg. 4(+34H) */
#define EATER_12NS		0
#define EATER_25NS		BIT7
#define EATER_35NS		BIT6
#define EATER_0NS		(BIT7+BIT6)
#define NEGATE_REQACKDATA	BIT2
#define NEGATE_REQACK		BIT3
/*
;====================
; DMA Register
;====================
*/
/*; DMA Command Reg.(+40H) */
#define READ_DIRECTION		BIT7
#define WRITE_DIRECTION 	0
#define EN_DMA_INT		BIT6
#define MAP_TO_MDL		BIT5
#define DIAGNOSTIC		BIT4
#define DMA_IDLE_CMD		0
#define DMA_BLAST_CMD		BIT0
#define DMA_ABORT_CMD		BIT1
#define DMA_START_CMD		(BIT1+BIT0)

/*; DMA Status Reg.(+54H) */
#define PCI_MS_ABORT		BIT6
#define BLAST_COMPLETE		BIT5
#define SCSI_INTERRUPT		BIT4
#define DMA_XFER_DONE		BIT3
#define DMA_XFER_ABORT		BIT2
#define DMA_XFER_ERROR		BIT1
#define POWER_DOWN		BIT0

/*
; DMA SCSI Bus and Ctrl.(+70H)
;EN_INT_ON_PCI_ABORT
*/

/*
;==========================================================
; SCSI Chip register address offset
;==========================================================
*/
#define CtcReg_Low	0x00
#define CtcReg_Mid	0x04
#define ScsiFifo	0x08
#define ScsiCmd 	0x0C
#define Scsi_Status	0x10
#define INT_Status	0x14
#define Sync_Period	0x18
#define Sync_Offset	0x1C
#define CtrlReg1	0x20
#define Clk_Factor	0x24
#define CtrlReg2	0x2C
#define CtrlReg3	0x30
#define CtrlReg4	0x34
#define CtcReg_High	0x38
#define DMA_Cmd 	0x40
#define DMA_XferCnt	0x44
#define DMA_XferAddr	0x48
#define DMA_Wk_ByteCntr 0x4C
#define DMA_Wk_AddrCntr 0x50
#define DMA_Status	0x54
#define DMA_MDL_Addr	0x58
#define DMA_Wk_MDL_Cntr 0x5C
#define DMA_ScsiBusCtrl 0x70

#define StcReg_Low	CtcReg_Low
#define StcReg_Mid	CtcReg_Mid
#define Scsi_Dest_ID	Scsi_Status
#define Scsi_TimeOut	INT_Status
#define Intern_State	Sync_Period
#define Current_Fifo	Sync_Offset
#define StcReg_High	CtcReg_High

#define am_target	Scsi_Status
#define am_timeout	INT_Status
#define am_seq_step	Sync_Period
#define am_fifo_count	Sync_Offset


#define DC390_read8(address)			       \
	inb(DC390_ioport + (address)))

#define DC390_read16(address)			       \
	inw(DC390_ioport + (address)))

#define DC390_read32(address)			       \
	inl(DC390_ioport + (address)))

#define DC390_write8(address,value)		       \
	outb((value), DC390_ioport + (address)))

#define DC390_write16(address,value)		       \
	outw((value), DC390_ioport + (address)))

#define DC390_write32(address,value)		       \
	outl((value), DC390_ioport + (address)))


/* Configuration method #1 */
#define PCI_CFG1_ADDRESS_REG		0xcf8
#define PCI_CFG1_DATA_REG		0xcfc
#define PCI_CFG1_ENABLE 		0x80000000
#define PCI_CFG1_TUPPLE(bus, device, function, register)		\
	(PCI_CFG1_ENABLE | (((bus) << 16) & 0xff0000) | 		\
	(((device) << 11) & 0xf800) | (((function) << 8) & 0x700)|	\
	(((register) << 2) & 0xfc))

/* Configuration method #2 */
#define PCI_CFG2_ENABLE_REG		0xcf8
#define PCI_CFG2_FORWARD_REG		0xcfa
#define PCI_CFG2_ENABLE 		0x0f0
#define PCI_CFG2_TUPPLE(function)					\
	(PCI_CFG2_ENABLE | (((function) << 1) & 0xe))


#endif /* TMSCSIM_H */