msp430dayii_dma_04.c

基于TI的MSP430的方面的相关的软件和MSP430的相关的资料.

//******************************************************************************
//  MSP-430-Day II Demo - DMA0 Block Mode UART0 9600, ACLK
//
//  Description; DMA0 is used to transfer a string as a block to U1TXBUF. 
//  UTXIFG1 WILL trigger DMA0. "Hello World" is TX'd via 9600 baud on UART1.
//  Watchdog in interval mode triggers block transfer every 1000ms.
//  Level senstive trigger used for UTXIFG0 to prevent loss of inital edge 
//  sensitive triggers - UTXIFG0 which is set at POR.
//  ACLK = UCLK 32768Hz, MCLK = SMCLK = default DCO ~ 800k
//  Baud rate divider with 32768hz XTAL @9600 = 32768Hz/9600 = 3.41 (000Dh 4Ah )
//  //*An external watch crystal on XIN XOUT is required for ACLK*//	  
//  //*Final Production MSP430F439 Device Required*//
//
//               MSP430FG439
//            -----------------
//        /|\|              XIN|-  
//         | |                 | 32768Hz
//         --|RST          XOUT|-
//           |                 |
//           |             P2.4|------------> "Hello World"
//           |                 | 9600 - 8N1
//
//  M.Buccini
//  Texas Instruments, Inc
//  February 2004
//  Built with IAR Embedded Workbench Version: 2.21B
//******************************************************************************

#include  "msp430xG43x.h"

static char string1[] = { "Hello World\r\n" };

void main(void)
{
  WDTCTL = WDT_ADLY_1000;                     // WDT 1000ms, ACLK, interval timer
  IE1 |= WDTIE;                               // Enable WDT interrupt
  P2SEL = 0x30;                               // P2.4,5 = USAR0 TXD/RXD
  ME1 |= UTXE0;                               // Enabled UART0 TXD
  U0CTL |= CHAR;                              // 8-bit char, SWRST=1
  U0TCTL |= SSEL0;                            // UCLK = ACLK
  U0BR0 = 0x03;                               // 9600 from 32768Hz
  U0BR1 = 0x00;
  U0MCTL = 0x4A;                              // Modulation
  U0CTL &= ~SWRST;                            // Enable USART
  DMACTL0 = DMA0TSEL_4;                       // UTXIFG0
  DMA0SA = (unsigned int)string1;             // Source block address
  DMA0DA = U0TXBUF_;                          // Dest single address
  DMA0SZ = sizeof string1-1;                  // Block size
  DMA0CTL = DMASRCINCR_3 + DMASBDB + DMALEVEL;     // inc src, byte

  _BIS_SR(LPM3_bits + GIE);                   // Enter LPM3 w/ interrupt
}
    
// Watchdog Timer interrupt service routine
#pragma vector=WDT_VECTOR
__interrupt void watchdog_timer(void)
{
  DMA0CTL |= DMAEN;                           // Enable
}