📄 stm32f10x_gpio.txt
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; generated by ARM C/C++ Compiler, 4.1 [Build 481]
; commandline ArmCC [--debug -c --asm --interleave -o.\OBJ\stm32f10x_gpio.o --depend=.\OBJ\stm32f10x_gpio.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\Demo -I.\HARDWARE\EXTI -I.\HARDWARE\KEY -I.\HARDWARE\LCD -I.\HARDWARE\LED -I.\HARDWARE\TIMER -I.\HARDWARE\WDG -I.\SYSTEM\delay -I.\SYSTEM\sys -I.\SYSTEM\usart -I.\USER -IC:\Keil\ARM\INC -IC:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\OBJ\stm32f10x_gpio.crf HARDWARE\stm32f10x_gpio.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
GPIO_DeInit PROC
;;;50 *******************************************************************************/
;;;51 void GPIO_DeInit(GPIO_TypeDef* GPIOx)
000000 b510 PUSH {r4,lr}
;;;52 {
000002 4604 MOV r4,r0
;;;53 /* Check the parameters */
;;;54 assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
;;;55
;;;56 switch (*(u32*)&GPIOx)
000004 49c5 LDR r1,|L1.796|
000006 1a60 SUBS r0,r4,r1
000008 428c CMP r4,r1
00000a d02f BEQ |L1.108|
00000c dc09 BGT |L1.34|
00000e 48c4 LDR r0,|L1.800|
000010 1820 ADDS r0,r4,r0
000012 d010 BEQ |L1.54|
000014 f5b06f80 CMP r0,#0x400
000018 d016 BEQ |L1.72|
00001a f5b06f00 CMP r0,#0x800
00001e d14a BNE |L1.182|
000020 e01b B |L1.90|
|L1.34|
000022 f5b06f80 CMP r0,#0x400
000026 d02a BEQ |L1.126|
000028 f5b06f00 CMP r0,#0x800
00002c d030 BEQ |L1.144|
00002e f5b06f40 CMP r0,#0xc00
000032 d140 BNE |L1.182|
000034 e035 B |L1.162|
|L1.54|
;;;57 {
;;;58 case GPIOA_BASE:
;;;59 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
000036 2101 MOVS r1,#1
000038 2004 MOVS r0,#4
00003a f7fffffe BL RCC_APB2PeriphResetCmd
;;;60 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
00003e 2100 MOVS r1,#0
000040 2004 MOVS r0,#4
000042 f7fffffe BL RCC_APB2PeriphResetCmd
;;;61 break;
000046 e037 B |L1.184|
|L1.72|
;;;62
;;;63 case GPIOB_BASE:
;;;64 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
000048 2101 MOVS r1,#1
00004a 2008 MOVS r0,#8
00004c f7fffffe BL RCC_APB2PeriphResetCmd
;;;65 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
000050 2100 MOVS r1,#0
000052 2008 MOVS r0,#8
000054 f7fffffe BL RCC_APB2PeriphResetCmd
;;;66 break;
000058 e02e B |L1.184|
|L1.90|
;;;67
;;;68 case GPIOC_BASE:
;;;69 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
00005a 2101 MOVS r1,#1
00005c 2010 MOVS r0,#0x10
00005e f7fffffe BL RCC_APB2PeriphResetCmd
;;;70 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
000062 2100 MOVS r1,#0
000064 2010 MOVS r0,#0x10
000066 f7fffffe BL RCC_APB2PeriphResetCmd
;;;71 break;
00006a e025 B |L1.184|
|L1.108|
;;;72
;;;73 case GPIOD_BASE:
;;;74 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
00006c 2101 MOVS r1,#1
00006e 2020 MOVS r0,#0x20
000070 f7fffffe BL RCC_APB2PeriphResetCmd
;;;75 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
000074 2100 MOVS r1,#0
000076 2020 MOVS r0,#0x20
000078 f7fffffe BL RCC_APB2PeriphResetCmd
;;;76 break;
00007c e01c B |L1.184|
|L1.126|
;;;77
;;;78 case GPIOE_BASE:
;;;79 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
00007e 2101 MOVS r1,#1
000080 2040 MOVS r0,#0x40
000082 f7fffffe BL RCC_APB2PeriphResetCmd
;;;80 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
000086 2100 MOVS r1,#0
000088 2040 MOVS r0,#0x40
00008a f7fffffe BL RCC_APB2PeriphResetCmd
;;;81 break;
00008e e013 B |L1.184|
|L1.144|
;;;82
;;;83 case GPIOF_BASE:
;;;84 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
000090 2101 MOVS r1,#1
000092 2080 MOVS r0,#0x80
000094 f7fffffe BL RCC_APB2PeriphResetCmd
;;;85 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
000098 2100 MOVS r1,#0
00009a 2080 MOVS r0,#0x80
00009c f7fffffe BL RCC_APB2PeriphResetCmd
;;;86 break;
0000a0 e00a B |L1.184|
|L1.162|
;;;87
;;;88 case GPIOG_BASE:
;;;89 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
0000a2 2101 MOVS r1,#1
0000a4 0208 LSLS r0,r1,#8
0000a6 f7fffffe BL RCC_APB2PeriphResetCmd
;;;90 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
0000aa 2100 MOVS r1,#0
0000ac f44f7080 MOV r0,#0x100
0000b0 f7fffffe BL RCC_APB2PeriphResetCmd
;;;91 break;
0000b4 e000 B |L1.184|
|L1.182|
;;;92
;;;93 default:
;;;94 break;
0000b6 bf00 NOP
|L1.184|
0000b8 bf00 NOP ;61
;;;95 }
;;;96 }
0000ba bd10 POP {r4,pc}
;;;97
ENDP
GPIO_AFIODeInit PROC
;;;106 *******************************************************************************/
;;;107 void GPIO_AFIODeInit(void)
0000bc b510 PUSH {r4,lr}
;;;108 {
;;;109 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
0000be 2101 MOVS r1,#1
0000c0 4608 MOV r0,r1
0000c2 f7fffffe BL RCC_APB2PeriphResetCmd
;;;110 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
0000c6 2100 MOVS r1,#0
0000c8 2001 MOVS r0,#1
0000ca f7fffffe BL RCC_APB2PeriphResetCmd
;;;111 }
0000ce bd10 POP {r4,pc}
;;;112
ENDP
GPIO_Init PROC
;;;123 *******************************************************************************/
;;;124 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
0000d0 e92d41f0 PUSH {r4-r8,lr}
;;;125 {
0000d4 4602 MOV r2,r0
;;;126 u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
0000d6 2500 MOVS r5,#0
0000d8 2600 MOVS r6,#0
0000da 2000 MOVS r0,#0
0000dc 2300 MOVS r3,#0
;;;127 u32 tmpreg = 0x00, pinmask = 0x00;
0000de 2400 MOVS r4,#0
0000e0 2700 MOVS r7,#0
;;;128
;;;129 /* Check the parameters */
;;;130 assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
;;;131 assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
;;;132 assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
;;;133
;;;134 /*---------------------------- GPIO Mode Configuration -----------------------*/
;;;135 currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
0000e2 f891c003 LDRB r12,[r1,#3]
0000e6 f00c050f AND r5,r12,#0xf
;;;136
;;;137 if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
0000ea f891c003 LDRB r12,[r1,#3]
0000ee f01c0f10 TST r12,#0x10
0000f2 d003 BEQ |L1.252|
;;;138 {
;;;139 /* Check the parameters */
;;;140 assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
;;;141 /* Output mode */
;;;142 currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
0000f4 f891c002 LDRB r12,[r1,#2]
0000f8 ea4c0505 ORR r5,r12,r5
|L1.252|
;;;143 }
;;;144
;;;145 /*---------------------------- GPIO CRL Configuration ------------------------*/
;;;146 /* Configure the eight low port pins */
;;;147 if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
0000fc f8b1c000 LDRH r12,[r1,#0]
000100 f01c0fff TST r12,#0xff
000104 d031 BEQ |L1.362|
;;;148 {
;;;149 tmpreg = GPIOx->CRL;
000106 6814 LDR r4,[r2,#0]
;;;150
;;;151 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
000108 2000 MOVS r0,#0
00010a e02b B |L1.356|
|L1.268|
;;;152 {
;;;153 pos = ((u32)0x01) << pinpos;
00010c f04f0c01 MOV r12,#1
000110 fa0cf300 LSL r3,r12,r0
;;;154 /* Get the port pins position */
;;;155 currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
000114 f8b1c000 LDRH r12,[r1,#0]
000118 ea0c0603 AND r6,r12,r3
;;;156
;;;157 if (currentpin == pos)
00011c 429e CMP r6,r3
00011e d120 BNE |L1.354|
;;;158 {
;;;159 pos = pinpos << 2;
000120 0083 LSLS r3,r0,#2
;;;160 /* Clear the corresponding low control register bits */
;;;161 pinmask = ((u32)0x0F) << pos;
000122 f04f0c0f MOV r12,#0xf
000126 fa0cf703 LSL r7,r12,r3
;;;162 tmpreg &= ~pinmask;
00012a 43bc BICS r4,r4,r7
;;;163
;;;164 /* Write the mode configuration in the corresponding bits */
;;;165 tmpreg |= (currentmode << pos);
00012c fa05fc03 LSL r12,r5,r3
000130 ea4c0404 ORR r4,r12,r4
;;;166
;;;167 /* Reset the corresponding ODR bit */
;;;168 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
000134 f891c003 LDRB r12,[r1,#3]
000138 f1bc0f28 CMP r12,#0x28
00013c d106 BNE |L1.332|
;;;169 {
;;;170 GPIOx->BRR = (((u32)0x01) << pinpos);
00013e f04f0c01 MOV r12,#1
000142 fa0cfc00 LSL r12,r12,r0
000146 f8c2c014 STR r12,[r2,#0x14]
00014a e00a B |L1.354|
|L1.332|
;;;171 }
;;;172 else
;;;173 {
;;;174 /* Set the corresponding ODR bit */
;;;175 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
00014c f891c003 LDRB r12,[r1,#3]
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