📄 sysend.c
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KS8695P_ENET_TERTIARY_BUF_ADRS
};
#endif /* KS8695P_ENET_FIXED_BUF_ADRS */
#ifdef INCLUDE_FEI82557END
LOCAL FEI_RESOURCE feiResources [KS8695P_MAX_END_DEVS] =
{
{UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,
UNKNOWN, UNKNOWN, {UNKNOWN}, UNKNOWN,
{UNKNOWN}, NULL, FEI_MEMSIZE0, FEI_INIT_STATE_MASK, FEI_INIT_STATE},
{UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,
UNKNOWN, UNKNOWN, {UNKNOWN}, UNKNOWN,
{UNKNOWN}, NULL, FEI_MEMSIZE0, FEI_INIT_STATE_MASK, FEI_INIT_STATE},
{UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,
UNKNOWN, UNKNOWN, {UNKNOWN}, UNKNOWN,
{UNKNOWN}, NULL, FEI_MEMSIZE0, FEI_INIT_STATE_MASK, FEI_INIT_STATE}
};
LOCAL const char * phys[] =
{
"None", "i82553-A/B", "i82553-C", "i82503",
"DP83840", "80c240", "80c24", "i82555",
"unknown-8", "unknown-9", "DP83840A", "unknown-11",
"unknown-12", "unknown-13", "unknown-14", "unknown-15"
};
enum phy_chips
{
NonSuchPhy=0, I82553AB, I82553C, I82503,
DP83840, S80C240, S80C24, I82555, DP83840A=10, UndefinedPhy
};
LOCAL const char *connectors[] = {" RJ45", " BNC", " AUI", " MII"};
#endif /* INCLUDE_FEI82557END */
/* imports */
/* End device table - should be KS8695P_MAX_END_DEVS+1 entries */
/* 05/13/2004 pcd
IMPORT END_TBL_ENTRY endDevTbl[];
*/
END_TBL_ENTRY feiEndDevTbl [] =
{
/* Entries that can be filled in dynamically when cards are found */
{ 0, END_TBL_END, NULL, 0, NULL, FALSE},
{ 0, END_TBL_END, NULL, 0, NULL, FALSE},
{ 0, END_TBL_END, NULL, 0, NULL, FALSE},
/* End of table marker */
{ 0, END_TBL_END, NULL, 0, NULL, FALSE}
};
#ifdef INCLUDE_DEC21X40END
/* DEC specific imports */
IMPORT END_OBJ * dec21x40EndLoad (char *, void *);
IMPORT int dec21x40Loops;
#endif
#ifdef INCLUDE_FEI82557END
/* FEI specific imports */
IMPORT FUNCPTR feiEndIntConnect;
IMPORT FUNCPTR feiEndIntDisconnect;
IMPORT END_OBJ* fei82557EndLoad (char *, void *);
IMPORT void sysFlashBoardDelay (void);
/* forward declarations */
LOCAL UINT16 sys557eepromRead (int unit, int location);
LOCAL UINT32 sys557mdioRead (int unit, int phyId, int location);
LOCAL UINT32 sys557mdioWrite (int unit, int phyId, int location, int value);
LOCAL int sys557IntEnable (int unit);
LOCAL int sys557IntDisable (int unit);
LOCAL int sys557IntAck (int unit);
#endif /* INCLUDE_FEI82557END */
/*******************************************************************************
*
* sysLanPciInit - prepare LAN adapter for initialization
*
* This routine find out the PCI device, and map its memory and I/O address.
* It will understand both DEC21x4x and FEI type cards.
*
* RETURNS: N/A
*/
STATUS sysLanPciInit (void)
{
PCI_RESOURCES * pRsrc; /* dec resource */
UINT32 pciBus; /* PCI Bus number */
UINT32 pciDevice; /* PCI Device number */
UINT32 pciFunc; /* PCI Function number */
unsigned int ix; /* counter */
int iy; /* counter */
int unit = 0; /* unit numbers */
UINT32 boardType = NONE; /* board type detected */
#ifdef INCLUDE_FEI82557END
FEI_RESOURCE * pFeiRes; /* FEI specific info */
#endif
#ifdef INCLUDE_DEC21X40END
/*
* Set the loops to be less per nano-second since this board is slower,
* than say, EBSA-285.
*/
dec21x40Loops = 1;
#endif
/*
* The following code tries to automatically detect and configure
* all instances of supported Ethernet cards.
*/
for (ix = 0; ix < BOARD_TYPE_NB; ix++)
{
for (iy = 0; iy < KS8695P_MAX_END_DEVS; iy++)
{
if (pciFindDevice ((int) boardResources[ix].vendorId,
(int) boardResources[ix].deviceId,
iy, (int *)&pciBus, (int *)(&pciDevice),
(int *)(&pciFunc)) != OK)
{
break; /* skip to next vendor/product pair */
}
/* board detected */
boardType = boardResources[ix].type;
/*
* Update the END device table
*
* pciDevice for PCI cards plugged in is in slot 5.
*/
pRsrc = &(pciResources[pciDevice - 5]);
if (pRsrc->configType == AUTO)
{
/* Assign resources (interrupt, I/O) */
pciAssignResources (pciBus, pciDevice, pciFunc);
/* get memory base address and I/O base address */
#ifdef INCLUDE_DEC21X40END
if ((boardType >= DEC_START) &&
(boardType < (DEC_START + TYPE_ALLOC)))
{
pciConfigInLong ((int)pciBus, (int)pciDevice, (int)pciFunc,
PCI_CFG_BASE_ADDRESS_0,
(int *)&pRsrc->iobaseCsr);
pciConfigInLong ((int)pciBus, (int)pciDevice, (int)pciFunc,
PCI_CFG_BASE_ADDRESS_1,
(int *)&pRsrc->membaseCsr);
pciConfigInByte ((int)pciBus, (int)pciDevice, (int)pciFunc,
PCI_CFG_DEV_INT_LINE, (char *)&pRsrc->irq);
pRsrc->membaseCsr &= ~CSR_BASE_MSK;
pRsrc->iobaseCsr &= ~CSR_BASE_MSK;
/* overwrite the resource table with read value */
pRsrc->irqvec = IVEC_TO_INUM(pRsrc->irq);
}
#endif /* INCLUDE_DEC21X40END */
#ifdef INCLUDE_FEI82557END
if ((boardType >= FEI_START) &&
(boardType < (FEI_START + TYPE_ALLOC)))
{
pFeiRes = &feiResources [unit];
pciConfigInLong ((int)pciBus, (int)pciDevice, (int)pciFunc,
PCI_CFG_BASE_ADDRESS_0,
(int *)&pFeiRes->membaseCsr);
/* Convert to CPU address */
pFeiRes->membaseCsr += PCI2CPU_MEM_OFFSET;
pciConfigInLong ((int)pciBus, (int)pciDevice, (int)pciFunc,
PCI_CFG_BASE_ADDRESS_1,
(int *)&pFeiRes->iobaseCsr);
pFeiRes->iobaseCsr &= ~PCI_BASE_IO;
pFeiRes->iobaseCsr += PCI2CPU_IO_OFFSET;
pciConfigInByte (pciBus, pciDevice, pciFunc,
PCI_CFG_DEV_INT_LINE,
&pFeiRes->irq);
}
#endif /* INCLUDE_FEI82557END */
}
else /* Force PCI configuration */
{
#ifdef INCLUDE_DEC21X40END
if ((boardType >= DEC_START) &&
(boardType < (DEC_START + TYPE_ALLOC)))
{
/* set memory base address and I/O base address */
pciConfigOutLong (pciBus, pciDevice, pciFunc,
PCI_CFG_BASE_ADDRESS_0,
pRsrc->iobaseCsr | PCI_BASE_IO);
pciConfigOutLong (pciBus, pciDevice, pciFunc,
PCI_CFG_BASE_ADDRESS_1,
pRsrc->membaseCsr);
pciConfigOutByte (pciBus, pciDevice, pciFunc,
PCI_CFG_DEV_INT_LINE, pRsrc->irq);
}
#endif /* INCLUDE_DEC21X40END */
#ifdef INCLUDE_FEI82557END
if ((boardType >= FEI_START) &&
(boardType < (FEI_START + TYPE_ALLOC)))
{
pFeiRes = &feiResources [unit];
pciConfigOutLong (pciBus, pciDevice, pciFunc,
PCI_CFG_BASE_ADDRESS_0,
pRsrc->membaseCsr);
pFeiRes->membaseCsr = pRsrc->membaseCsr + PCI2CPU_MEM_OFFSET;
pciConfigOutLong (pciBus, pciDevice, pciFunc,
PCI_CFG_BASE_ADDRESS_1,
pRsrc->iobaseCsr | PCI_BASE_IO);
pFeiRes->iobaseCsr = pRsrc->iobaseCsr + PCI2CPU_IO_OFFSET;
pciConfigOutByte (pciBus, pciDevice, pciFunc,
PCI_CFG_DEV_INT_LINE, pRsrc->irq);
pFeiRes->irq = pRsrc->irq;
}
#endif /* INCLUDE_FEI82557END */
} /* if (pRsrc->configType == AUTO) */
/*
* Update the END device table & dynamically create the load
* string we need for this device
*/
#ifdef INCLUDE_DEC21X40END
if ((boardType >= DEC_START) &&
(boardType < (DEC_START + TYPE_ALLOC)))
{
/*
* END load string format:
* "<deviceAddr>:<pciAddr>:<iVec>:<iLevel>:<numRds>:<numTds>:\
* <memBase>:<memSize>:<userFlags>:<phyAddr>:<pPhyTbl>:\
* <phyFlags>:<offset>"
*/
#ifdef KS8695P_ENET_FIXED_BUF_ADRS
pRsrc->buf = (void *)sysEnetBufAdrs [unit];
pRsrc->cpuToPciOffset = 0;
#else /* KS8695P_ENET_FIXED_BUF_ADRS */
pRsrc->cpuToPciOffset = PCI2DRAM_BASE_ADRS;
#ifdef KS8695P_ENET_CHECK_BUFFERS
if (pRsrc->buf = cacheDmaMalloc (KS8695P_DEC_BUF_SIZE),
pRsrc->buf == NULL)
{
/* cannot log msg at this point in initialisation timeline*/
return ERROR;
}
#else /* KS8695P_ENET_CHECK_BUFFERS */
pRsrc->buf = (void *)NONE;
#endif /* KS8695P_ENET_CHECK_BUFFERS */
#endif /* KS8695P_ENET_FIXED_BUF_ADRS */
sprintf (endLoadStr[currentEndDevice],
"%#x:%#x:%#x:%#x:-1:-1:%#x:%#x:%#x:%#x:%#x:%#x:2:-1:0:",
/* Note: unit is prepended by the mux driver */
pRsrc->iobaseCsr + PCI2CPU_IO_OFFSET, /*devAdrs*/
pRsrc->cpuToPciOffset, /*pciMemBase*/
pRsrc->irq, pRsrc->irqvec, /*ivec,ilevel*/
/* numRds=default, numTds=default */
(UINT32)pRsrc->buf, /*memBase*/
KS8695P_DEC_BUF_SIZE, /*memSize*/
boardResources[ix].decUsrFlags, /*usrFlags*/
1, 0, /* phyAddr,pMiiPhyTbl,*/
DEC_USR_MII_10MB |
DEC_USR_MII_HD | DEC_USR_MII_100MB |
DEC_USR_MII_FD | DEC_USR_MII_BUS_MON
);
endDevTbl[currentEndDevice].unit = unit++;
endDevTbl[currentEndDevice].endLoadFunc = dec21x40EndLoad;
endDevTbl[currentEndDevice].endLoadString =
endLoadStr[currentEndDevice];
endDevTbl[currentEndDevice].endLoan = DEC_BUFF_LOAN;
currentEndDevice++;
/* enable mapped memory and I/O addresses */
pciConfigOutWord (pciBus, pciDevice, pciFunc, PCI_CFG_COMMAND,
PCI_CMD_IO_ENABLE | PCI_CMD_MASTER_ENABLE);
/* disable sleep mode */
pciConfigOutByte (pciBus, pciDevice, pciFunc, PCI_CFG_MODE,
SLEEP_MODE_DIS);
}
#endif /* INCLUDE_DEC21X40END */
#ifdef INCLUDE_FEI82557END
if ((boardType >= FEI_START) &&
(boardType < (FEI_START + TYPE_ALLOC)))
{
#ifdef KS8695P_ENET_FIXED_BUF_ADRS
pRsrc->buf = (void *)sysEnetBufAdrs [unit];
#else /* KS8695P_ENET_FIXED_BUF_ADRS */
#ifdef KS8695P_ENET_CHECK_BUFFERS
if (pRsrc->buf = cacheDmaMalloc (KS8695P_FEI_BUF_SIZE),
pRsrc->buf == NULL)
{
/* cannot log msg at this point in initialisation timeline*/
return ERROR;
}
#else /* KS8695P_ENET_CHECK_BUFFERS */
pRsrc->buf = (void *)NONE;
#endif /* KS8695P_ENET_CHECK_BUFFERS */
#endif /* KS8695P_ENET_FIXED_BUF_ADRS */
sprintf (endLoadStr[currentEndDevice],
"0x%08X:0x%08X:0x%X:0x%X:0x00:2",
(UINT32)pRsrc->buf, KS8695P_FEI_BUF_SIZE,
KS8695P_FEI_NUM_CFDS, KS8695P_FEI_NUM_RFDS);
/*
Micrel used endDevTbl for ks8695p END driver. for PCI bus interface, used
fei END driver as example, which will use new 'endDevTbl', call 'feiEndDevTbl'.
endDevTbl[currentEndDevice].unit = unit++;
endDevTbl[currentEndDevice].endLoadFunc = fei82557EndLoad;
endDevTbl[currentEndDevice].endLoadString =
endLoadStr[currentEndDevice];
endDevTbl[currentEndDevice].endLoan = 1;
*/
feiEndDevTbl[currentEndDevice].unit = unit++;
feiEndDevTbl[currentEndDevice].endLoadFunc = fei82557EndLoad;
feiEndDevTbl[currentEndDevice].endLoadString =
endLoadStr[currentEndDevice];
feiEndDevTbl[currentEndDevice].endLoan = 1;
currentEndDevice++;
/* enable mapped I/O addresses */
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