📄 syslib.c
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/* sysLib.c - KS8695P demo board system-dependent routines */
/*
modification history
--------------------
V1.09:---------------------------------------------------------------------
05/13/2004 pcd
(1).Integrate KS8695/KS8695X to KS8695P. Different features are on following ('x' as support):
WAN LAN HPNA PCI FlowCntl SDRAM WAN_PHY(0xEA14)
KS8695 x x x 16MB 0xB000
KS8695X x x 16MB 0xB000
KS8695P x x x x 32MB 0x0 (default)
The default is is for KS8695P
The definition "KS8695" is for KS8695
The definition "KS8695X" is for KS8695X
(2).PCI space memory can't "CACHEABLE".
(3).for MMU with System Configuration Regs space, just simply defined one 64K block.
---------------------------------------------------------------------
9/15/2003 Ritter Yeh created
*/
/*
DESCRIPTION
This library provides board-specific routines for the KS8695P
Demo Board BSP.
It #includes the following chip drivers:
ks8695pTimer.c - KS8695P timer driver
ks8695pIntrCtl.c - KS8695P interrupt controller driver
ks8695plSio.c - KS8695P UART driver
pciIomapLib.c - PCI I/O mapping support
if INCLUDE_FLASH is defined, it #includes:
flashMem.c - Flash memory driver
nvRamToFlash.c - driver to use some Flash like NVRAM
else it #includes:
nullNvRam.c - dummy NVRAM routines
It #includes the following BSP files:
sysSerial.c - serial device initialisation routines
for KS8695P only
sysEnd.c - END network driver support routines.
pciIomapShow.c - PCI Show routines
INCLUDE FILES:
for KS8695P
sysLib.h string.h intLib.h taskLib.h vxLib.h muxLib.h
pciIomapLib.h
for KS8695/X
sysLib.h string.h intLib.h taskLib.h vxLib.h muxLib.h
*/
/* includes */
#include "vxWorks.h"
#include "config.h"
#include "sysLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "muxLib.h"
#include "cacheLib.h"
#include "arch/arm/mmuArmLib.h"
#include "private/vmLibP.h"
#include "dllLib.h"
#include "pciIomapLib.h"
/* imports */
IMPORT char end []; /* end of system, created by ld */
IMPORT VOIDFUNCPTR _func_armIntStackSplit; /* ptr to fn to split stack */
#if !defined(INCLUDE_MMU) && \
(defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU_BASIC) || \
defined(INCLUDE_MMU_FULL) || defined(INCLUDE_MMU_MPU))
#define INCLUDE_MMU
#endif
/* globals */
/*
* a variable "local_mem_size" indicates the memory size by
* if "KS8695 || KS8695X || KS8695P" board.
* KS8695P: local_mem_size = 0x02000000 (32MB)
* KS8695X: local_mem_size = 0x01000000 (16MB)
* KS8695 : local_mem_size = 0x01000000 (16MB)
*/
#if defined(KS8695) || defined(KS8695X)
UINT local_mem_size = 0x01000000; /* 16 Mbytes for KS8695/X */
#else
UINT local_mem_size = 0x02000000; /* 32 Mbytes for KS8695P */
#endif
#if defined(INCLUDE_MMU)
/*
* The following structure describes the various different parts of the
* memory map to be used only during initialisation by
* vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC/FULL are
* defined.
*
* Clearly, this structure is only needed if the CPU has an MMU!
*
* The following are not the smallest areas that could be allocated for a
* working system. If the amount of memory used by the page tables is
* critical, they could be reduced.
*/
PHYS_MEM_DESC sysPhysMemDesc [] =
{
/* DRAM must always be the first entry */
/* adrs and length parameters must be page-aligned (multiples of 0x1000) */
/* DRAM - Always the first entry */
#if defined(KS8695) || defined(KS8695X) /* KS8695/KS8695X */
{ /* 0x0000-0000 */
(void *) LOCAL_MEM_LOCAL_ADRS, /* virtual address */
(void *) LOCAL_MEM_LOCAL_ADRS, /* physical address */
ROUND_UP (LOCAL_MEM_SIZE, PAGE_SIZE), /* length (16MB SDRAM), then initial state: */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
/*RLQ, for debug with all SDRAM set to no cacheable
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
*/
},
#else /* KS8695P, 326MB SDRAM */
{ /* 0x0000-0000 */
(void *) LOCAL_MEM_LOCAL_ADRS, /* virtual address */
(void *) LOCAL_MEM_LOCAL_ADRS, /* physical address */
ROUND_UP ((2*LOCAL_MEM_SIZE), PAGE_SIZE), /* length (32MB SDRAM), then initial state: */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
/*RLQ, for debug with all SDRAM set to no cacheable
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
*/
},
#endif
/*
* ROM is normally marked as uncacheable by VxWorks. We leave it like that
* for the time being, even though this has a severe impact on execution
* speed from ROM.
*/
{ /* 0x0280-0000 */
(void *) ROM_BASE_ADRS,
(void *) ROM_BASE_ADRS,
ROUND_UP (ROM_SIZE_TOTAL, PAGE_SIZE),
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
/* I/O and memory control registers , simply defined one 64K block */
{
(void *) REG_IO_BASE,
(void *) REG_IO_BASE,
ROUND_UP (REG_IO_SIZE, PAGE_SIZE),
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
#if (0) /* 05/13/2004 pcd */
/* I/O and memory control registers */
{ /* 0x03FF-0000 */
(void *) REG_IO_BASE,
(void *) REG_IO_BASE,
PAGE_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
/*PCI-AHB Bridge Configuration registers */
{ /* 0x03FF-2000 */
(void *) (REG_IO_BASE+REG_PCI_CRCFID),
(void *) (REG_IO_BASE+REG_PCI_CRCFID),
PAGE_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
/*Memory control registers */
{ /* 0x03FF-4000 */
(void *) (REG_IO_BASE+REG_IO_CTRL0),
(void *) (REG_IO_BASE+REG_IO_CTRL0),
PAGE_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
/*WAN control registers */
{ /* 0x03FF-6000 */
(void *) (REG_IO_BASE+REG_WAN_DMA_TX),
(void *) (REG_IO_BASE+REG_WAN_DMA_TX),
PAGE_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
/*LAN control registers */
{ /* 0x03FF-8000 */
(void *) (REG_IO_BASE+REG_LAN_DMA_TX),
(void *) (REG_IO_BASE+REG_LAN_DMA_TX),
PAGE_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
/*UART, Interrupt, Timer, GPIO, SWITCH, PHY control registers */
{ /* 0x03FF-E000 */
(void *) (REG_IO_BASE+REG_UART_RX_BUFFER),
(void *) (REG_IO_BASE+REG_UART_RX_BUFFER),
PAGE_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
#endif /* #if (0) */
#if !defined(KS8695) && !defined(KS8695X) /* KS8695P only */
#ifdef INCLUDE_PCI
{ /* 0x8000-0000 */
(void *) CPU_PCI_IO_ADRS, /* PCI I/O space */
(void *) CPU_PCI_IO_ADRS,
ROUND_UP (CPU_PCI_IO_SIZE, PAGE_SIZE),
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
/* 05/13/2004 pcd
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
*/
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
{ /* 0x6000-0000 */
(void *) CPU_PCI_MEM_ADRS, /* PCI Mem space */
(void *) CPU_PCI_MEM_ADRS,
ROUND_UP (CPU_PCI_MEM_SIZE, PAGE_SIZE),
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
/* 05/13/2004 pcd
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
*/
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
#endif /* INCLUDE_PCI */
#endif /* #if !defined(KS8695) && !defined(KS8695X) */
};
int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);
#endif /* defined(INCLUDE_MMU) */
int sysBus = BUS; /* system bus type (VME_BUS, etc) */
int sysCpu = CPU; /* system CPU type (e.g. ARMARCH4/4_T)*/
char * sysBootLine = BOOT_LINE_ADRS; /* address of boot line */
char * sysExcMsg = EXC_MSG_ADRS; /* catastrophic message area, for ARM offset is LOCAL_MEM_LOCAL_ADRS + 0x800 */
int sysProcNum; /* processor number of this CPU */
int sysFlags; /* boot flags */
char sysBootHost [BOOT_FIELD_LEN]; /* name of host from which we booted */
char sysBootFile [BOOT_FIELD_LEN]; /* name of file from which we booted */
/* locals */
/* defines */
#undef MINI_PCI
/* externals */
IMPORT int ambaIntDevInit (void);
IMPORT void sysIntStackSplit (char *, long);
/* globals */
/* forward LOCAL functions declarations */
/* forward declarations */
char * sysPhysMemTop (void);
#if defined (INCLUDE_USB)
void sysUsbPciInit(void);
#endif
/* included source files */
#ifdef INCLUDE_FLASH
#include "mem/nvRamToFlash.c"
#include "flashMem.c"
#else
#include "mem/nullNvRam.c"
#endif
#include "vme/nullVme.c"
#include "sysSerial.c"
#include "ks8695Timer.c"
#include "ks8695IntrCtl.c"
#include "ks8695Sio.c"
#if !defined(KS8695) && !defined(KS8695X) /* KS8695P only */
#include "pciIomapLib.c"
#include "pciIomapShow.c"
#include "sysEnd.c"
#endif /* #if !defined(KS8695) && !defined(KS8695X) */
#include "ks8695End.c"
#include "sysKS8695End.c"
#if !defined(KS8695) && !defined(KS8695X) /* KS8695P only */
IMPORT STATUS pciDeviceShow (int);
void pciScan (void)
{
pciDeviceShow (0);
}
void pciSetFei (void)
{
pciConfigOutLong (0, 5, 0, PCI_CFG_COMMAND, 0x00000007);
}
#endif /* #if !defined(KS8695) && !defined(KS8695X) */
/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* NOTE
* This routine does not include all of the possible variants, and the
* inclusion of a variant in here does not mean that it is supported.
*
* RETURNS: A pointer to a string identifying the board and CPU.
*/
char *sysModel (void)
{
#ifdef KS8695
return "Micrel KS8695";
#else
#ifdef KS8695X
return "Micrel KS8695X";
#else
return "MICREL KS8695P ";
#endif
#endif
}
/*******************************************************************************
*
* sysBspRev - return the BSP version with the revision eg 1.2/<x>
*
* This function returns a pointer to a BSP version with the revision.
* e.g. 1.2/<x>. BSP_REV is concatenated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/
char * sysBspRev (void)
{
return (BSP_VERSION BSP_REV);
}
/*******************************************************************************
*
* sysHwInit0 - perform early BSP-specific initialisation
*
* This routine performs such BSP-specific initialisation as is necessary before
* the architecture-independent cacheLibInit can be called. It is called
* from usrInit() before cacheLibInit(), before sysHwInit() and before BSS
* has been cleared.
*
* RETURNS: N/A
*/
void sysHwInit0 (void)
{
#ifdef INCLUDE_CACHE_SUPPORT
/*
* Install the appropriate cache library, no address translation
* routines are required for this BSP, as the default memory map has
* virtual and physical addresses the same.
*/
cacheArm920tLibInstall (NULL, NULL);
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