📄 rominit.s
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/* romInit.s - KS8695P demo board ROM initialization module */
/* Copyright 1999-2001 Wind River Systems, Inc. */
/*
modification history
--------------------
06/01/2004 PCD In order to write to flash easier, don't enable read/write FIFO
in the ks8695 Memory Controller.
9/22/2003 Ritter Yeh created
*/
/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'. The entry
point, romInit(), is the first code executed on power-up. It performs
the minimal setup needed to call the generic C routine romStart() with
parameter BOOT_COLD.
romInit() masks interrupts in the processor and the interrupt
controller and sets the initial stack pointer (to STACK_ADRS which is
defined in configAll.h). Other hardware and device initialisation is
performed later in the sysHwInit routine in sysLib.c.
The routine sysToMonitor() jumps to a location after the beginning of
romInit, (defined by ROM_WARM_ADRS) to perform a "warm boot". This
entry point allows a parameter to be passed to romStart().
The routines in this module don't use the "C" frame pointer %r11@ ! or
establish a stack frame.
*/
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "regs.h"
#include "config.h"
#include "arch/arm/mmuArmLib.h"
.data
.globl VAR(copyright_wind_river)
.long VAR(copyright_wind_river)
/* internals */
.globl FUNC(romInit) /* start of system code */
.globl VAR(sdata) /* start of data */
.globl _sdata
.globl VAR(boardActualMemSize) /* actual memory size */
/* externals */
.extern FUNC(romStart) /* system initialization routine */
_sdata:
VAR_LABEL(sdata)
.asciz "start of data"
.balign 4
/* variables */
.data
VAR_LABEL(boardActualMemSize)
.long 0
.text
.balign 4
/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* romInit
* (
* int startType /@ only used by 2nd entry point @/
* )
* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*/
_ARM_FUNCTION(romInit)
_romInit:
cold:
MOV r0, #BOOT_COLD /* fall through to warm boot entry */
warm:
B start
/* copyright notice appears at beginning of ROM (in TEXT segment) */
.ascii "Copyright 2003 Micrel, Inc."
.ascii "\nCopyright 1999-2001 Wind River Systems, Inc."
.balign 4
start:
/*
* Set processor and MMU to known state as follows (we may have not
* been entered from a reset). We must do this before setting the CPU
* mode as we must set PROG32/DATA32.
*
* MMU Control Register layout.
*
* bit
* 0 M 0 MMU disabled
* 1 A 0 Address alignment fault disabled, initially
* 2 C 0 Data cache disabled
* 3 W 0 Write Buffer disabled
* 4 P 1 PROG32
* 5 D 1 DATA32
* 6 L 1 Should Be One (Late abort on earlier CPUs)
* 7 B 0 Endianness (1 => little)
* 8 S 0 System bit to zero } Modifies MMU protections, not really
* 9 R 1 ROM bit to one } relevant until MMU switched on later.
* 10 F 0 Should Be Zero
* 11 Z 0 Should Be Zero (Branch prediction control on 810)
* 12 I 0 Instruction cache control
*/
/* Setup MMU Control Register */
MOV r1, #MMU_INIT_VALUE /* Defined in mmuArmLib.h */
MCR CP_MMU, 0, r1, c1, c0, 0 /* Write to MMU CR */
/*
* If MMU was on before this, then we'd better hope it was set
* up for flat translation or there will be problems. The next
* 2/3 instructions will be fetched "translated" (number depends
* on CPU).
*
* We would like to discard the contents of the Write-Buffer
* altogether, but there is no facility to do this. Failing that,
* we do not want any pending writes to happen at a later stage,
* so drain the Write-Buffer, i.e. force any pending writes to
* happen now.
*/
MOV r1, #0 /* data SBZ */
MCR CP_MMU, 0, r1, c7, c10, 4 /* drain write-buffer */
/* Flush (invalidate) both I and D caches */
MCR CP_MMU, 0, r1, c7, c7, 0 /* R1 = 0 from above, data SBZ*/
/*
* Set Process ID Register to zero, this effectively disables
* the process ID remapping feature.
*/
MOV r1, #0
MCR CP_MMU, 0, r1, c13, c0, 0
/* disable interrupts in CPU and switch to SVC32 mode */
LDR r4, =REG_IO_BASE /* load register base address */
LDR r5, =REG_INT_ENABLE
ADD r5, r5, r4
LDR r8, =INIT_INT
STR r8, [r5]
MRS r1, cpsr
BIC r1, r1, #MASK_MODE
ORR r1, r1, #MODE_SVC32 | I_BIT | F_BIT
MSR cpsr, r1
/* --- Initialise stack pointer registers, no memory can be accessed at
this time. */
/* Enter ABT mode and set up the ABT stack pointer */
MRS r1, cpsr
BIC r1, r1, #MASK_MODE
ORR r1, r1, #MODE_ABT | I_BIT | F_BIT
MSR cpsr, r1
LDR SP, =ABT_STACK
/* Enter UNDEF mode and set up the UNDEF stack pointer */
MRS r1, cpsr
BIC r1, r1, #MASK_MODE
ORR r1, r1, #MODE_UNDEF | I_BIT | F_BIT
LDR SP, =UNDEF_STACK
/* Enter FIQ mode and set up the FIQ stack pointer */
MRS r1, cpsr
BIC r1, r1, #MASK_MODE
ORR r1, r1, #MODE_FIQ | I_BIT | F_BIT
LDR SP, =FIQ_STACK
/* Enter IRQ mode and set up the IRQ stack pointer */
MRS r1, cpsr
BIC r1, r1, #MASK_MODE
ORR r1, r1, #MODE_IRQ | I_BIT | F_BIT
LDR SP, =IRQ_STACK
/* Enter SVC mode and set up the SVC stack pointer */
MRS r1, cpsr
BIC r1, r1, #MASK_MODE
ORR r1, r1, #MODE_SVC | I_BIT | F_BIT
LDR SP, =SVC_STACK
/* Enter SYS mode and set up the SYS stack pointer for temperary use */
MRS r1, cpsr
BIC r1, r1, #MASK_MODE
ORR r1, r1, #MODE_SYS | I_BIT | F_BIT
LDR SP, =RAM_LIMIT_TMP
LDR r4, =REG_IO_BASE /* load register base address */
LDR r5, =REG_SDRAM_CTRL0 /* set up SDRAM bank 0 */
ADD r5, r5, r4
LDR r8, =TMP_SDRAM_REG0
STR r8, [r5]
LDR r5, =REG_SDRAM_CTRL1 /* set up SDRAM bank 1 */
ADD r5, r5, r4
LDR r8, =TMP_SDRAM_REG1
STR r8, [r5]
/* set up SDRAM control */
LDR r5, =REG_SDRAM_GENERAL
ADD r5, r5, r4
LDR r8, =SDRAM_RASCAS
STR r8, [r5]
/* set up SDRAM buffer control */
LDR r5, =REG_SDRAM_BUFFER
ADD r5, r5, r4
LDR r8, =SDRAM_NOP_COMD /* send NOP command */
STR r8, [r5]
LDR r7, =SDRAM_NOP_COMD
sr01:
LDR r8, [r5]
ANDS r8, r8, r7
BNE sr01
NOP
LDR r8, =SDRAM_PRECHARGE_CMD /* send precharge command */
STR r8, [r5]
sr02:
LDR r8, [r5]
LDR r7, =SDRAM_NOP_COMD
ANDS r8, r8, r7
BNE sr02
NOP
/* set up SDRAM refresh timer */
LDR r5, =REG_SDRAM_REFRESH
ADD r5, r5, r4
MOV r8, #20 /* quick refresh at least twice */
STR r8, [r5] /* before sending Mode command */
/* wait for two refresh to complete */
MOV r8, #10
sr05:
SUBS r8, r8, #1
BNE sr05
NOP
LDR r8, =SDRAM_REFRESH_TIMER /* set back normal refresh timer */
STR r8, [r5]
LDR r5, =REG_SDRAM_BUFFER
ADD r5, r5, r4
LDR r8, =SDRAM_MODE_COMD /* send Mode command */
STR r8, [r5]
sr03:
LDR r8, [r5]
ANDS r8, r8, r7
BNE sr03
NOP
/*========================================================
; Here is memory remapping code,
; First copy two instuctions to SDRAM and jump to the
; first, the second intruction will jump the pc back to
; remapped flash.
;======================================================== */
LDR r5, =REG_MEM_CTRL0
ADD r5, r5, r4 /* remapp rom bank 0 start at 0x02800000 */
LDR r8, =REM_FLASH_REG
STMFD r13!, {r3-r6}
ADR r3, map_instruc
LDR r4, =SDRAM_START
LDMIA r3, {r5-r6}
STMIA r4, {r5-r6}
LDMFD r13!, {r3-r6}
ADR r10, jump_to_here
LDR r1, =FLASH_ROM_START
ADD r10, r10, r1
LDR pc, =SDRAM_START
map_instruc:
STR r8, [r5]
MOV pc, r10
HiPosn:
jump_to_here:
LDR r5, =REG_SDRAM_BUFFER
ADD r5, r5, r4
LDR r8, =SDRAM_PRECHARGE_CMD /* send precharge command */
STR r8, [r5]
j107:
LDR r8, [r5]
LDR r7, =SDRAM_NOP_COMD
ANDS r8, r8, r7
BNE j107
NOP
LDR r5, =REG_SDRAM_CTRL0 /* set up SDRAM bank 0 */
ADD r5, r5, r4
LDR r8, =REM_SDRAM_REG0
STR r8, [r5]
LDR r5, =REG_SDRAM_CTRL1 /* set up SDRAM bank 1 */
ADD r5, r5, r4
LDR r8, =REM_SDRAM_REG1
STR r8, [r5]
/* enable all the ext i/o flash and rom banks */
LDR r5, =REG_MEM_GENERAL
ADD r5, r5, r4
LDR r8, =ROM_GENERAL_SETTING
STR r8, [r5]
/* change system clock here if you need more speed. */
LDR r5, =REG_SYSTEN_BUS_CLOCK
ADD r5, r5, r4
LDR r8, =SYSTEN_BUS_CLOCK_125
STR r8, [r5]
LDR r5, =REG_GPIO_DATA
ADD r5, r5, r4
LDR r1, =INIT_GPIO_DATA
STR r1, [r5]
LDR r5, =REG_GPIO_CTRL
ADD r5, r5, r4
LDR r1, =INIT_GPIO_CTRL
STR r1, [r5]
/* set the MODE register last to */
LDR r5, =REG_GPIO_MODE
ADD r5, r5, r4
LDR r1, =INIT_GPIO_MODE
STR r1, [r5]
/* enable FIFO write and read */
/* 06/01/2004 PCD : don't disable read\write FIFO */
#LDR r5, =REG_SDRAM_BUFFER
#ADD r5, r5, r4
#LDR r8, =0x1F00000 /* enable FIFOs */
#STR r8, [r5]
/* disable interrupts in CPU and switch to SVC32 mode */
MRS r1, cpsr
BIC r1, r1, #MASK_MODE
ORR r1, r1, #MODE_SVC32 | I_BIT | F_BIT
MSR cpsr, r1
/* r1 now contains memory size: store this in Memory_Size variable */
LDR r1, =SDRAM_TOTAL_SIZE
LDR r3, L$_memSize
STR r1, [r3]
MOV r3, r1 /* Need to return size in both these registers*/
/*
* Initialize the stack pointer to just before where the
* uncompress code, copied from ROM to RAM, will run.
*/
LDR sp, L$_STACK_ADDR
MOV fp, #0 /* zero frame pointer */
LDR r5, =REG_GPIO_DATA
ADD r5, r5, r4
LDR r1, =0x00008000
STR r1, [r5]
/* jump to C entry point in ROM: routine - entry point + ROM base */
LDR pc, L$_rStrtInRom
/******************************************************************************/
/*
* PC-relative-addressable pointers - LDR Rn,=sym is broken
* note "_" after "$" to stop preprocessor performing substitution
*/
.balign 4
L$_HiPosn:
.long ROM_TEXT_ADRS + HiPosn - FUNC(romInit)
L$_rStrtInRom:
.long ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)
L$_STACK_ADDR:
.long STACK_ADRS
L$_memSize:
.long VAR(boardActualMemSize)
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