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📄 ks8695end.h

📁 这是micrel公司宽带路由ARM9芯片的VXWORKS BSP 源代码
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	LED_LINK_ACTIVITY,	/* link/activities */
} LED_SELECTOR;

/* register Bit field for Switch control 0 */
#define	SW_CTRL0_AUTO_FAST_AGING	 0x00100000	/* automic fast aging when link changed detected */
#define	SW_CTRL0_ERROR_PKT		0x00080000		/* pass all error packets */
#define	SW_CTRL0_ENABLE_PORT5	0x00040000		/* enable port 5 flow control */
#define	SW_CTRL0_ENABLE_PORTS	0x00020000		/* enable flow control for port 1 - 4 */
#define	SW_CTRL0_BUFFER_SHARE	0x00010000		/* buffer share mode */
#define	SW_CTRL0_AGING_ENABLE	0x00008000		/* aging enable */
#define	SW_CTRL0_FAST_AGING		0x00004000		/* fast aging enable */
#define	SW_CTRL0_FAST_BACKOFF	0x00002000		/* fast back off */
#define	SW_CTRL0_MISMATCH_DISCARD	 0x00001000	/* VLAN mismatch discard */
#define	SW_CTRL0_NO_BCAST_STORM_PROT 0x00000800	/* no broadcast storm proection tp ,cast pkts */
#define	SW_CTRL0_PREAMBLE_MODE	0x00000400		/* back pressure mode */
#define	SW_CTRL0_FLOWCTRL_FAIR	0x00000200		/* flow control fair mode */
#define	SW_CTRL0_COLLISION_DROP	0x00000100		/* no excessive collision drop */
#define	SW_CTRL0_LEN_CHECKING	0x00000080		/* enforced max length checking */
#define	SW_CTRL0_6K_BUFFER		0x00000040		/* 6K byte buffer per port reserved for high priority pkts */
#define	SW_CTRL0_BACK_PRESSURE	0x00000020		/* back pressure enable */
#define	SW_CTRL0_SWITCH_ENABLE	0x00000001		/* enable switch bit */

/* register Bit field for Auto Regotiation */
#define	SW_AUTONEGO_COMPLETE	0x00004000		/* auto nego completed */
#define	SW_AUTONEGO_RESTART		0x00002000		/* auto nego restart */
#define	SW_AUTONEGO_ADV_PUASE	0x00001000		/* auto nego advertise PAUSE */
#define	SW_AUTONEGO_ADV_100FD	0x00000800		/* auto nego advertise 100 FD */
#define	SW_AUTONEGO_ADV_100HD	0x00000400		/* auto nego advertise 100 HD */
#define	SW_AUTONEGO_ADV_10FD	0x00000200		/* auto nego advertise 10 FD */
#define	SW_AUTONEGO_ADV_10HD	0x00000100		/* auto nego advertise 10 HD */
#define	SW_AUTONEGO_STAT_LINK	0x00000080		/* auto nego link status */
#define	SW_AUTONEGO_STAT_DUPLEX	0x00000040		/* auto nego duplex status (solved) */
#define	SW_AUTONEGO_STAT_SPEED	0x00000020		/* auto nego speed status (solved) */
#define	SW_AUTONEGO_PART_PAUSE	0x00000010		/* auto nego parterner pause */
#define	SW_AUTONEGO_PART_100FD	0x00000008		/* auto nego parterner 100 FD */
#define	SW_AUTONEGO_PART_100HD	0x00000004		/* auto nego parterner 100 HD */
#define	SW_AUTONEGO_PART_10FD	0x00000002		/* auto nego parterner 10 FD */
#define	SW_AUTONEGO_PART_10HD	0x00000001		/* auto nego parterner 10 HD */

#define	SW_AUTONEGO_ADV_MASK	0x00001f00

#define	SW_MAX_LAN_PORTS		4				/* max LAN ports */

/* bits for SNMP data register (SEMCD) */
#ifndef	CONFIG_ARCH_KS8695P
#define	SW_SNMP_DATA_VALID		0x80000000		/* counter value is valid */
#define	SW_SNMP_DATA_OVERFLOW	0x40000000		/* counter is overflow */
#else
#define	SW_SNMP_DATA_OVERFLOW	0x80000000		/* counter is overflow */
#define	SW_SNMP_DATA_VALID		0x40000000		/* counter value is valid */
#endif

enum PORTS {
	SW_PORT_1 = 0,
	SW_PORT_2,
	SW_PORT_3,
	SW_PORT_4
};

/* bits related to power management */
#define	POWER_POWERDOWN			0x00000010		/* port power down */
#define	POWER_DMDX_DISABLE		0x00000008		/* disable auto MDI/MDIX */
#define	POWER_FORCE_MDIX		0x00000004		/* if auto MDI/MDIX is disabled, force PHY into MDIX mode */
#define	POWER_LOOPBACK			0x00000002		/* PHY loopback */

#define SW_PHY_AUTO				0               /* autosense */
#define SW_PHY_10BASE_T			1               /* 10Base-T */
#define SW_PHY_10BASE_T_FD		2               /* 10Base-T Full Duplex */
#define SW_PHY_100BASE_TX		3               /* 100Base-TX */
#define SW_PHY_100BASE_TX_FD	4               /* 100Base-TX Full Duplex */

#define SW_PHY_DEFAULT			SW_PHY_AUTO

enum SPANNINGTREE {
	SW_SPANNINGTREE_NONE,		                /* no spanning tree */
	SW_SPANNINGTREE_RX,			                /* spanning tree, RX only */
	SW_SPANNINGTREE_TX,			                /* spanning tree, TX only */
	SW_SPANNINGTREE_ALL,		                /* spanning tree, both TX/RX */
};

/* bits related to port configuration register */
#define	SW_PORT_DISABLE_AUTONEG	0x00008000		/* port disable auto nego */
#define	SW_PORT_100BASE			0x00004000		/* force 100 when auto nego disabled */
#define	SW_PORT_FULLDUPLEX		0x00002000		/* force full duplex when auto nego disabled */
#define	SW_PORT_TX_SPANNINGTREE	0x00000080		/* spanning tree transmit enable */
#define	SW_PORT_RX_SPANNINGTREE	0x00000040		/* spanning tree receive enable */
#define	SW_PORT_NO_SPANNINGTREE	0x00000020		/* spanning tree disable */
#define	SW_PORT_STORM_PROCTION	0x00000010		/* broadcast storm protection (ingress) */
#define	SW_PORT_HI_PRIORITY		0x00000008		/* high priority (ingress) */
#define	SW_PORT_TOS_ENABLE		0x00000004		/* Enable TOS based priotiry classification (ingress) */
#define	SW_PORT_8021Q_ENABLE	0x00000002		/* Enable 802.1Q based priotiry classification (ingress) */
#define	SW_PORT_PRIOTIRY_ENABLE	0x00000001		/* Enable priotiry function on the port (egress) */

/* port 5 only */
#define	SW_PORT_RX_DIRECT_MODE	0x00004000		/* receive direct mode for port 5 */
#define	SW_PORT_TX_PRETAG_MODE	0x00002000		/* transmit pre-tag mode for port 5 */

typedef struct _PORT_INFO {
    UINT16 usTag;				                /* tag value for the port (ingress) */
	UINT8 byCrossTalkMask;		                /* specify ports that this port can talk to */
	UINT8 byStormProtection;	                /* broadcast storm protection */
	UINT8 bySpanningTree;		                /* spanning tree */
	UINT8 byDisableSpanningTreeLearn;	        /* disable spanning tree learn for the port */
	UINT8 byIngressPriority;	                /* ingress priority */
	UINT8 byIngressPriorityTOS;	                /* TOS based ingress priority */
	UINT8 byIngressPriority802_1P;              /* 802.1p based ingress priority */
	UINT8 byEgressPriority;		                /* egress priority */
} PORT_INFO, *PPORT_INFO;

/* defined original from ioctrl */
/*
 * local defines
 */
enum {
	REG_DMA_DUMP,			/* dump all base DMA registers (based on current driver is for) */
	REG_DMA_STATION_DUMP,	/* dump all DMA extra station registers */
	REG_UART_DUMP,			/* dump all UART related registers */
	REG_INT_DUMP,			/* dump all Interrupt related registers */
	REG_TIMER_DUMP,			/* dump all Timer related registers */
	REG_GPIO_DUMP,			/* dump all GPIO related registers */
	REG_SWITCH_DUMP,		/* dump all Switch related registers */
	REG_MISC_DUMP,			/* dump all misc registers */
	REG_SNMP_DUMP,			/* dump all SNMP registers */

	DRV_VERSION,			/* get driver version, (we need this since proc is removed from driver) */

	DUMP_PCI_SPACE,			/* dump PCI configuration space for KS8695P */
	DUMP_BRIDGE_REG,		/* dump bridge related register for KS8695P */

	MEMORY_DUMP,			/* to dump given memory */
	MEMORY_SEARCH,			/* to search for given data pattern */

	REG_WRITE,				/* to write IO register */

	DEBUG_DUMP_TX_PACKET,	/* to debug ethernet packet to transmit */
	DEBUG_DUMP_RX_PACKET,	/* to debug ethernet packet received */

	DEBUG_RESET_DESC,		/* to reset Rx descriptors */
	DEBUG_STATISTICS,		/* debug statistics */
	DEBUG_DESCRIPTORS,		/* debug descriptors */

	DEBUG_LINK_STATUS,		/* debug link status */

	CONFIG_LINK_TYPE,		/* configure link media type */
	CONFIG_STATION_EX,		/* configure additional station */

	/* switch configuration for web page */
	CONFIG_SWITCH_GET,		/* get switch configuration settings */
	CONFIG_SWITCH_SET,		/* set switch configuration settings */
};

/* defined configured SWITCH SUBID */
enum CONFIG_SWITCH_SUBID {
	/* configuration related to basic switch web page */
	CONFIG_SW_SUBID_ON,					/* turn on/off switch for LAN */
	CONFIG_SW_SUBID_PORT_VLAN,			/* configure port VLAN ID, and Engress mode */
	CONFIG_SW_SUBID_PRIORITY,			/* configure port priority */

	/* configuration related to advanced switch web page */
	CONFIG_SW_SUBID_ADV_LINK_SELECTION,	/* configure port link selection */
	CONFIG_SW_SUBID_ADV_CTRL,			/* configure switch control register */
	CONFIG_SW_SUBID_ADV_MIRRORING,		/* configure switch port mirroring */
	CONFIG_SW_SUBID_ADV_THRESHOLD,		/* configure threshold for both 802.1p and broadcast storm protection */
	CONFIG_SW_SUBID_ADV_DSCP,			/* configure switch DSCP priority */

	/* configuration related to Switch internal web page */
	CONFIG_SW_SUBID_INTERNAL_LED,			/* configure LED for all */
	CONFIG_SW_SUBID_INTERNAL_MISC,			/* configure misc. */
	CONFIG_SW_SUBID_INTERNAL_SPANNINGTREE,	/* configure spanning tree */

	/* configuration phy related features for KS8695P */
	CONFIG_SW_SUBID_PHY_IF,				/* configure PHY interface, for KS8695P only */
	CONFIG_SW_SUBID_SEC1,				/* configure Switch Engine Control 1 register 0xE804 */

	/* for KS8695P only */
	CONFIG_SW_SUBID_GENERIC_DUMP,		/* generic dump for KS8695), e.g. Dynamic Mac Table, or switch registers */
	CONFIG_SW_SUBID_RATE_CTRL,			/* high/low priority rate control */
};

enum  GENERIC_DUMP {
	GENERIC_DUMP_STATIC,		/* dump static Mac table */
	GENERIC_DUMP_DYNAMIC,		/* dump dynamic Mac table */
	GENERIC_DUMP_VLAN,			/* dump VLAN table */
	GENERIC_DUMP_SWITCH_REGS,	/* dump switch registers for KS8695P */
};

/* defined configured SWITCH SUBID */
enum _DEBUG_PACKET {		/* debug packet bit definition */
	DEBUG_PACKET_LEN	= 0x00000001,		/* debug packet length */
	DEBUG_PACKET_HEADER	= 0x00000002,		/* debug packet header */
	DEBUG_PACKET_CONTENT	= 0x00000004,	/* debug packet content */
	DEBUG_PACKET_OVSIZE	= 0x00000008,		/* dump rx over sized packet content */
	DEBUG_PACKET_UNDERSIZE	= 0x00000010,	/* prompt rx under sized packet */
};

enum _LINK_SELECTION {
	LINK_SELECTION_FULL_AUTO = 0,		/* fully auto nego */
	LINK_SELECTION_FORCED,				/* forced mode, no auto nego */
	LINK_SELECTION_PARTIAL_AUTO,		/* partial auto nego */
};

#define SPEED_UNKNOWN					0
#define SPEED_10						10
#define SPEED_100						100
#define FULL_DUPLEX						1		/* default for full duplex */
#define HALF_DUPLEX						0

#define	REG_DMA_MAX				8
#define	REG_DMA_STATION_MAX		32
#define	REG_UART_MAX			9
#define	REG_INT_MAX				14
#define	REG_TIMER_MAX			5
#define	REG_GPIO_MAX			3
#define	REG_SWITCH_MAX			21
#define	REG_MISC_MAX			7
#define	REG_SNMP_MAX			138

#define	DUMP_BUFFER_MAX			1024

#define SW_PHY_AUTO				0   /* autosense */
#define SW_PHY_10BASE_T			1   /* 10Base-T */
#define SW_PHY_10BASE_T_FD		2   /* 10Base-T Full Duplex */
#define SW_PHY_100BASE_TX		3   /* 100Base-TX */
#define SW_PHY_100BASE_TX_FD	4   /* 100Base-TX Full Duplex */

typedef struct _DMA_INFO {
	unsigned short	usDMAId;	/* DMAID */
	INT32	nBaseAddr;			/* base address */
	INT32	nOffset;			/* DMA register offset */
	UINT8	bUseFIQ;			/* use FIQ or not */
    UINT32 *pbaseVa;
	UINT32 nResetCount;			/* DMA reset counter */

	/* interrupt related */
	UINT32 uIntMask;			/* interrupt mask checked within ISR */
	UINT32 uLinkIntMask;		/* WAN link interrupt mask checked within ISR */
	UINT32 uIntShift;			/* interrupt bit shift */

	/* mac */
    UINT8 stMacStation[MAC_ADDRESS_LEN];
    UINT8 stMacCurrent[MAC_ADDRESS_LEN];
    UINT8 stSwitchMac[MAC_ADDRESS_LEN];

	/* semaphore */
	SEM_ID	txSem;				/* tx semaphore */
	SEM_ID	rxSem;				/* rx semaphore */
	SEM_ID	linkSem;			/* link semaphore */
	SEM_ID	intSem;				/* int semaphore */

	/* Tx related */
	UINT8	bTxStarted;			/* Tx DMA started or stopped! */
	UINT8	bTxFlowCtrl;		/* flow control for Tx DMA */
	UINT8	bTxOffLoad;			/* enable/disable Task offload for Tx DMA */
	UINT8	byTxPBL;			/* Tx PBL */
    UINT8   bTxChecksum;		/* checksum enable/disable indicator */
	UINT8	bTxNoResource;		/* flag indicates out of Tx resource */
	UINT32  uDebugDumpTxPkt;	/* flag to dump tx packet for debugging */

	/* Tx desc related */
	INT32	nTxDesc;			/* number of Tx descriptors */
    INT32   nTxDescNextAvail;	/* next available Tx descriptor */
    INT32   nTxDescUsed;		/* used Tx descriptor */
    volatile INT32 nTransmitCount;	/* number of packets to transmit */
    INT32   nTxProcessedCount;	/* number of packets to transmitted */
	INT32	nTxDescTotal;		/* total number fo Tx descriptors */
    INT32   nTransmitCoalescing;/* Tx packets coalescing count */

    TXDESC *pTxDescriptors;
	UINT32	TxDescDMA;
    CL_POOL_ID pClPoolId;		/* cluster pool id */
    volatile INT32 nTxDescAvail;
    struct ks8695_buffer *pTxMblk;

	/* Rx related */
	UINT8	bRxStarted;			/* Rx DMA started or stopped! */
	UINT8	bRxFlowCtrl;		/* flow control for Rx DMA */
	UINT8	bPort5FlowCtrl;		/* flow control for LAN port 5 */
	UINT8	bPortsFlowCtrl;		/* flow control for LAN port 1 - 4 */
	UINT8	byRxPBL;			/* Rx PBL */
    UINT8   bRxChecksum;		/* checksum enable/disable indicator */
    UINT32  uRxBufferLen;		/* rx buffer length */
	UINT32  uDebugDumpRxPkt;	/* flag to dump rx packet for debugging */
	UINT32  uRx1518plus;		/* rx packet counter for 1518 plus for debugging */
	UINT32  uRxUnderSize;		/* rx packet counter for under size packets (< 64) */
	UINT32  nMaxFilledCount;	/* max refilled count */
	UINT32  nMaxProcessedCount;	/* max rx pkt count in one process cycle */

    INT32   nRxDesc;			/* number of Rx descriptors */
    INT32   nRxDescNextAvail;	/* next available Rx descriptor */
    INT32   nRxDescNextToFill;	/* next Rx desc to fill new buffer to */
    RXDESC *pRxDescriptors;
	UINT32	RxDescDMA;
    volatile INT32 RxDescEmpty;	/* atomic flag for empty Rx descriptor  */
	INT32	nRxDescTotal;		/* total number fo Rx descriptors */
    struct ks8695_buffer *pRxMblk;

	/* PHY related */
	UINT8	bAutoNegoInProgress[SW_MAX_LAN_PORTS];  /* if set, means that auto nego is in progress!!! */
	UINT8	bLinkActive[SW_MAX_LAN_PORTS];		    /* flag indicates whether link is active or not */
    UINT8   bLinkChanged[SW_MAX_LAN_PORTS];		    /* link changed indicator */
    UINT8   bHalfDuplex[SW_MAX_LAN_PORTS];		    /* HD/FD */
	UINT16  usCType[SW_MAX_LAN_PORTS];			    /* Convert type */
    UINT16  usLinkSpeed[SW_MAX_LAN_PORTS];		    /* link speed */
	PORT_INFO	port[SW_MAX_LAN_PORTS + 1];		    /* port related */
	INT32	nLinkChangeCount;					    /* trace link change count */
	UINT8	byDisableAutoNego[SW_MAX_LAN_PORTS];	/* auto nego/disable auto nego/partial auto nego */
    UINT8   bHalfDuplexDetected[SW_MAX_LAN_PORTS];	/* HD/FD detected based on partner's settings */

	UINT8	bRxDirectMode;		/* for port 5 only */
	UINT8	bTxRreTagMode;		/* for port 5 only */

	UINT8 bPowerDownReset;		/* perform powerdown reset instead of soft reset */

} DMA_INFO, *PDMA_INFO;

/* socket buffer */
struct ks8695_buffer {
    M_BLK_ID 	pMblk;
};

typedef struct _INTCFG {
	UINT8	bFIQ;		/* use FIQ */
	UINT8	byPriority;	/* priority level for IRQ */
} INTCFG, *PINTCFG;

#define	DI		(pDrvCtrl->stDMAInfo)		/* Dma Information */
#define	DPI		(pDrvCtrl->stDMAInfo.port)	/* Dma Port Inforamtion */

#define	KS8695_READ_REG(reg)			KS8695P_REG(reg)				
#define	KS8695_WRITE_REG(reg, value)	KS8695P_REG(reg) = (value)


#ifdef	KS8695                 
#define	KS8695_MAX_END_DEVS		3		/* WAN/LAN/EMAC (for KS8695) */
#else              
#define	KS8695_MAX_END_DEVS		2		/* WAN/LAN (for KS8695X/KS8695P) */
#endif

enum dump_set {
	SET_DMA_DUMP			= 0x00000001,
	SET_DMA_STATION_DUMP	= 0x00000002,
	SET_UART_DUMP			= 0x00000004,
	SET_INT_DUMP			= 0x00000008,
	SET_TIMER_DUMP			= 0x00000010,
	SET_GPIO_DUMP			= 0x00000020,
	SET_SWITCH_DUMP			= 0x00000040,
	SET_MISC_DUMP			= 0x00000080,
	SET_SNMP_DUMP			= 0x00000100,
};

#ifdef __cplusplus
}
#endif

#endif /* __INCKS8695END_H */

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