📄 ks8695end.h
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/* ks8695End.h - END Ethernet driver header for KS8695/X/P SOHO router */
/* Copyright 1998-2002 Wind River Systems, Inc. */
/*
* Copyright (c) 2002-2003, Micrel Semiconductor
*
* Written 2003 by LIQUN RUAN (RLQ)
*
*
* The author may be reached as liqun.ruan@micrel.com
* Micrel Semiconductor
* 1931 Fortune Dr.
* San Jose, CA 95131
*
* This END Ethernet driver is for Micrel's KS8695/KS8695X/KS8695P SOHO Router Chipset.
*/
/*
modification history
--------------------
V1.09:---------------------------------------------------------------------
05/13/2004 pcd
(1).Integrate KS8695/KS8695X to KS8695P. They have different features on following ('x' as support):
WAN LAN HPNA PCI FlowCntl SDRAM WAN_PHY(0xEA14)
KS8695 x x x 16MB 0xB000
KS8695X x x 16MB 0xB000
KS8695P x x x x 32MB 0x0 (default)
The default is is for KS8695P
The definition "KS8695" is for KS8695
The definition "KS8695X" is for KS8695X
(2) Since KS8695P has problem generated IP/TCP/UDP checksum, diable
HW generats IP/TCP/UDP checksum.
V1.08:---------------------------------------------------------------------
11/25/2003, PCD, Increase TXDESC_DEFAULT from 32 to 48, RXDESC_DEFAULT from 64 to 128.
09/18/2003, RLQ, First created for KS8695/P SOHO Router END ethernet driver
*/
#ifndef __INCKS8695END_H
#define __INCKS8695END_H
#ifdef __cplusplus
extern "C" {
#endif
#include "end.h"
#include "cacheLib.h"
#include "netinet/if_ether.h"
/* define the various levels of debugging if the DRV_DEBUG is defined */
#ifdef DRV_DEBUG
# include "logLib.h"
#endif /* DRV_DEBUG */
/* board level/bus specific and architecture specific macros */
#if _BYTE_ORDER==_BIG_ENDIAN
# define PCI_SWAP(x) ((ks8695BusEndianess) ? (int)(x) : LONGSWAP((int)(x)))
#else
# define PCI_SWAP(x) (x)
#endif
#if _BYTE_ORDER==_BIG_ENDIAN
# define REG_SWAP(d,x) (((d)->flags & LS_MODE_NOSWAP_MASTER) ? \
(int)(x) : LONGSWAP((int)(x)))
#else
# define REG_SWAP(d,x) (x)
#endif
/* Configuration items */
typedef struct
{
UINT collisions;
UINT crcs;
UINT aligns;
UINT missed;
UINT overruns;
UINT disabled;
UINT deferring;
UINT underruns;
UINT aborts;
UINT outofwindow;
UINT heartbeats;
UINT badPacket;
UINT shortPacket;
UINT tnoerror;
UINT rnoerror;
UINT terror;
UINT rerror;
UINT overwrite;
UINT wrapped;
UINT interrupts;
UINT intLink;
UINT intTxComp;
UINT intRxAvail;
UINT intTxUnavail;
UINT intRxUnavail;
UINT intTxStop;
UINT intRxStop;
UINT reset;
UINT strayint;
UINT jabber;
} KS8695_STAT;
/* for KS8695X/KS8695P */
#define KS8695_DRV_WAN 0
#define KS8695_DRV_LAN 1
#define KS8695_DRV_MAX (KS8695_DRV_LAN + 1)
/* for KS8695 */
#ifdef KS8695
#define KS8695_DRV_HPNA 2 /* emac interface for KS8695 only */
#undef KS8695_DRV_MAX
#define KS8695_DRV_MAX (KS8695_DRV_HPNA + 1)
#endif
#define TRUE 1
#define FALSE 0
#ifndef BOOLEAN
#define BOOLEAN UINT8
#endif
/* command line options defaults */
#define TXDESC_DEFAULT 64
#define TXDESC_MAX 128
#define TXDESC_MIN 32
#define RXDESC_DEFAULT 128
#define RXDESC_MAX 128
#define RXDESC_MIN 32
/*06/10/2004, PCD
#define RXCHECKSUM_DEFAULT TRUE
#define TXCHECKSUM_DEFAULT TRUE
*/
#define RXCHECKSUM_DEFAULT FALSE
#define TXCHECKSUM_DEFAULT FALSE
#define FLOWCONTROL_DEFAULT TRUE
#define PBL_DEFAULT 8 /* 0 for unlimited, other value for (4 * x) */
/* Supported RX Buffer Sizes */
#define BUFFER_1568 1568 /* 0x620 */
#define BUFFER_2048 2048 /* 0x800 */
#define BUFFER_4K 4096 /* for KS8695 jumbo frame only */
/* standard ethernet header */
#define ENET_HEADER_SIZE 14
#define MAXIMUM_ETHERNET_PACKET_SIZE 1514
#define MINIMUM_ETHERNET_PACKET_SIZE 60
#define ETH_CRC_LENGTH 4
#define ETH_LENGTH_OF_ADDRESS 6
#define KS8695_ROUNDUP(size, unit) ((unit) * (((size) + (unit) - 1) / (unit)))
#ifndef BIT
#define BIT(x) (1L << (x))
#endif
#ifndef REG_MISC_CONTROL
#define REG_MISC_CONTROL 0xEA08
#endif
/* DMA related register offset */
#define REG_TXCTRL 0x0000
#define REG_RXCTRL 0x0004
#define REG_TXSTART 0x0008
#define REG_RXSTART 0x000c
#define REG_TXBASE 0x0010
#define REG_RXBASE 0x0014
#define REG_STATION_LOW 0x0018
#define REG_STATION_HIGH 0x001c
#define REG_MAC0_LOW 0x0080
#define REG_MAC0_HIGH 0x0084
#define REG_MAC1_LOW 0x0088
#define REG_MAC1_HIGH 0x008c
#define REG_MAC2_LOW 0x0090
#define REG_MAC2_HIGH 0x0094
#define REG_MAC3_LOW 0x0098
#define REG_MAC3_HIGH 0x009c
#define REG_MAC4_LOW 0x00a0
#define REG_MAC4_HIGH 0x00a4
#define REG_MAC5_LOW 0x00a8
#define REG_MAC5_HIGH 0x00ac
#define REG_MAC6_LOW 0x00b0
#define REG_MAC6_HIGH 0x00b4
#define REG_MAC7_LOW 0x00b8
#define REG_MAC7_HIGH 0x00bc
#define REG_MAC8_LOW 0x00c0
#define REG_MAC8_HIGH 0x00c4
#define REG_MAC9_LOW 0x00c8
#define REG_MAC9_HIGH 0x00cc
#define REG_MAC10_LOW 0x00d0
#define REG_MAC10_HIGH 0x00d4
#define REG_MAC11_LOW 0x00d8
#define REG_MAC11_HIGH 0x00dc
#define REG_MAC12_LOW 0x00e0
#define REG_MAC12_HIGH 0x00e4
#define REG_MAC13_LOW 0x00e8
#define REG_MAC13_HIGH 0x00ec
#define REG_MAC14_LOW 0x00f0
#define REG_MAC14_HIGH 0x00f4
#define REG_MAC15_LOW 0x00f8
#define REG_MAC15_HIGH 0x00fc
/* register Bit field defines for Tx Ctrl and (some are shared with RX) */
#define DMA_SOFTRESET 0x80000000 /* DMA soft reset (shared with RX) */
#define DMA_UDPCHECKSUM 0x00040000 /* bit 18 (shared with RX) */
#define DMA_TCPCHECKSUM 0x00020000 /* bit 17 (shared with RX) */
#define DMA_IPCHECKSUM 0x00010000 /* bit 16 (shared with RX) */
#define DMA_FLOWCTRL 0x00000200 /* bit 9 (shared with RX) */
#define DMA_LOOPBACK 0x00000100 /* bit 8 */
#define DMA_ERRORFRAME 0x00000008 /* bit 3 */
#define DMA_PADDING 0x00000004 /* bit 2 */
#define DMA_CRC 0x00000002 /* bit 1 */
#define DMA_START 0x00000001 /* bit 0 (shared with RX) */
#define DMA_PBLTMASK 0x3f000000 /* DMA Burst Size bit mask (shared with RX) */
#define DMA_PBLTSHIFT 24 /* DMA Burst Size bit shift */
/* some bits for RX Ctrl register */
#define DMA_BROADCAST 0x00000040 /* bit 6 */
#define DMA_MULTICAST 0x00000020 /* bit 5 */
#define DMA_UNICAST 0x00000010 /* bit 4 */
#define DMA_PROMISCUOUS 0x00000004 /* bit 2 */
/* Addition station registers */
#define DMA_MACENABLE 0x80000000 /* enable/disable additional MAC station address */
enum DMAID {
DMA_WAN = 0x6000, /* WAN DMA */
DMA_LAN = 0x8000, /* LAN DMA */
#ifdef KS8695
DMA_HPNA= 0xA000 /* HPNA DMA */
#endif
};
/* DESC and Data buffer */
#ifdef _CACHE_ALIGN_SIZE
#define DESC_ALIGNMENT _CACHE_ALIGN_SIZE
#else
#define DESC_ALIGNMENT 16 /* two dwords */
#endif
#define RXDESC_LOAN_NUM 2 /* max loaning for Rx */
/* Receive Descriptor */
typedef struct
{
volatile UINT32 RxFrameControl;
volatile UINT32 RxDMAFragLen;
volatile UINT32 RxDMAFragAddr;
volatile UINT32 RxDMANextPtr;
} RXDESC, *PRXDESC;
#define DESC_OWN_BIT 0x80000000 /* shared with Tx descriptor */
/* In Linux, we use all 32 bits definitions! */
/* Bits related to RxFrameControl */
#define RFC_FS 0x40000000 /* First Descriptor of the received frame */
#define RFC_LS 0x20000000 /* Last Descriptor of the received frame */
#define RFC_IPE 0x10000000 /* IP checksum generation */
#define RFC_TCPE 0x08000000 /* TCP checksum generation */
#define RFC_UDPE 0x04000000 /* UDP checksum generation */
#define RFC_ES 0x02000000 /* Error Summary */
#define RFC_MF 0x01000000 /* Multicast Frame */
#define RFC_RE 0x00080000 /* Report on MII/GMII error */
#define RFC_TL 0x00040000 /* Frame Too Long */
#define RFC_RF 0x00020000 /* Runt Frame */
#define RFC_CRC 0x00010000 /* CRC error */
#define RFC_FT 0x00008000 /* Frame Type */
#define RFC_SPN_MASK 0x00f00000 /* Switch engine destination port map, 20:23 */
#define RFC_FL_MASK 0x000007ff /* Frame Length bit mask, 0:10 */
#define RFC_FRAMECTRL_MASK (RFC_FS | RFC_LS | RFC_ES | RFC_MF | RFC_RE | RFC_TL | RFC_CRC | RFC_FT | RFC_FL_MASK)
/* Bits related to RxDMAFragLen */
#define RFC_RER 0x02000000 /* Receive End of Ring */
#define RFC_RBS_MASK 0x000007ff /* Receive buffer Size bit mask, 0:10 */
/* Transmit descriptor */
typedef struct
{
volatile UINT32 TxOwnBit;
volatile UINT32 TxFrameControl;
volatile UINT32 TxDMAFragAddr;
volatile UINT32 TxDMANextPtr;
} TXDESC, *PTXDESC;
/* Bits related to TxFrameControl */
#define TFC_IC 0x80000000 /* Interrupt on completion */
#define TFC_FS 0x40000000 /* first segment */
#define TFC_LS 0x20000000 /* last segment */
#define TFC_IPCKG 0x10000000 /* IP checksum generation */
#define TFC_TCPCKG 0x08000000 /* TCP checksum generation */
#define TFC_UDPCKG 0x04000000 /* UDP checksum generation */
#define TFC_TER 0x02000000 /* Transmit End of Ring */
#define TFC_SPN_MASK 0x00f00000 /* Switch engine destination port map, 20:23 */
#define TFC_TBS_MASK 0x000007ff /* Transmit Buffer Size Mask (0:10) */
#define TFC_FRAMECTRL_MASK (TFC_IC | TFC_FS | TFC_LS | TFC_SPN_MASK | TFC_TBS_MASK)
/* Interrupt related (shared among IMR, IER, ISR, IPR, and IQR) */
#define INT_WAN_LINK 0x80000000 /* WAN link change interrupt */
#define INT_WAN_TX 0x40000000 /* WAN Tx complete interrupt */
#define INT_WAN_RX 0x20000000 /* WAN Rx complete interrupt */
#define INT_WAN_TX_UNAVIAL 0x10000000 /* WAN Tx desc unavailable interrupt */
#define INT_WAN_RX_UNAVIAL 0x08000000 /* WAN Rx desc unavailable interrupt */
#define INT_WAN_TX_STOPPED 0x04000000 /* WAN Tx stopped interrupt */
#define INT_WAN_RX_STOPPED 0x02000000 /* WAN Rx stopped interrupt */
#define INT_WAN_MASK 0x7e000000 /* only Enable these WAN interrupt bit */
#define INT_AMBA_BUS_ERROR 0x01000000 /* AMBA bus error interrupt */
#define INT_HPNA_TX 0x00800000 /* HPNA Tx complete interrupt */
#define INT_HPNA_RX 0x00400000 /* HPNA Rx complete interrupt */
#define INT_HPNA_TX_UNAVIAL 0x00200000 /* HPNA Tx desc unavailable interrupt */
#define INT_HPNA_RX_UNAVIAL 0x00100000 /* HPNA Rx desc unavailable interrupt */
#define INT_HPNA_TX_STOPPED 0x00080000 /* HPNA Tx stopped interrupt */
#define INT_HPNA_RX_STOPPED 0x00040000 /* HPNA Rx stopped interrupt */
#define INT_HPNA_MASK 0x00fc0000
#define INT_LAN_TX 0x00020000 /* LAN Tx complete interrupt */
#define INT_LAN_RX 0x00010000 /* LAN Rx complete interrupt */
#define INT_LAN_TX_UNAVIAL 0x00008000 /* LAN Tx desc unavailable interrupt */
#define INT_LAN_RX_UNAVIAL 0x00004000 /* LAN Rx desc unavailable interrupt */
#define INT_LAN_TX_STOPPED 0x00002000 /* LAN Tx stopped interrupt */
#define INT_LAN_RX_STOPPED 0x00001000 /* LAN Rx stopped interrupt */
#define INT_LAN_MASK 0x0003f000 /* only Enable these LAN interrupt bit */
#define INT_DMA_MASK 0xfefff000 /* interrupt bit mask for DMA (WAN, HPNA and LAN) */
#define INT_DMA_STOP_MASK (INT_WAN_TX_STOPPED | INT_WAN_RX_STOPPED | INT_HPNA_TX_STOPPED | INT_HPNA_RX_STOPPED | INT_LAN_TX_STOPPED | INT_LAN_RX_STOPPED)
#define INT_TX_BIT BIT(5)
#define INT_RX_BIT BIT(4)
#define INT_TX_UNAVAIL_BIT BIT(3)
#define INT_RX_UNAVAIL_BIT BIT(2)
#define INT_TX_STOPPED_BIT BIT(1)
#define INT_RX_STOPPED_BIT BIT(0)
/* MAC address */
#define MAC_ADDRESS_LEN 6
typedef enum {
LED_SPEED, /* 0 */
LED_LINK,
LED_FD, /* full duplex */
LED_COLLISION,
LED_ACTIVITY,
LED_FD_COLLISION, /* full duplex/collision */
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