📄 ks8695p.h
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/* Advance Feature Control */
#define REG_SWITCH_ADVANCED 0xE860
/* TOS Priority */
#define REG_TOS_HIGH 0xE864
#define REG_TOS_LOW 0xE868
/* Switch Enagine MAC Address */
#define REG_SWITCH_MAC_HIGH 0xE86C
#define REG_SWITCH_MAC_LOW 0xE870
/* LAN PHY Power Management */
#define REG_LAN12_POWERMAGR 0xE874
#define REG_LAN34_POWERMAGR 0xE878
/* Digital Testing Status and Control */
#define REG_DIG_TEST 0xE87C
#define REG_ANA_TEST 0xE880
#else /* #if !defined(KS8695) && !defined(KS8695X) */
/* KS8695/KS8695X only */
/* Switch Enagine Control */
#define REG_SWITCH_CTRL0 0xE800
#define REG_SWITCH_CTRL1 0xE804
/* Port 1-4 and 5 Configuration Register Set 1 */
#define KS8695_SWITCH_PORT1 0xE808
#define KS8695_SWITCH_PORT2 0xE80C
#define KS8695_SWITCH_PORT3 0xE810
#define KS8695_SWITCH_PORT4 0xE814
#define KS8695_SWITCH_PORT5 0xE818
/* Auto Negotiation */
#define REG_SWITCH_AUTO0 0xE81C
#define REG_SWITCH_AUTO1 0xE820
/* Look-up Engine Indirect Access */
#define KS8695_SWITCH_LUE_CTRL 0xE824
#define KS8695_SWITCH_LUE_HIGH 0xE828
#define KS8695_SWITCH_LUE_LOW 0xE82C
/* Advance Feature Control */
#define REG_SWITCH_ADVANCED 0xE830
/* DHCP */
#define REG_TOS_HIGH 0xE834
#define REG_TOS_LOW 0xE838
/* switch Enagine MAC Address */
#define REG_SWITCH_MAC_HIGH 0xE83C
#define REG_SWITCH_MAC_LOW 0xE840
/* Management Counter Indirect Access */
#define KS8695_MANAGE_COUNTER 0xE844
#define KS8695_MANAGE_DATA 0xE848
/* LAN PHY Power Management */
#define REG_LAN12_POWERMAGR 0xE84C
#define REG_LAN34_POWERMAGR 0xE850
/* Digital Testing Status and Control */
#define REG_DIG_TEST 0xE87C
#define REG_ANA_TEST 0xE880
#endif /* #if !defined(KS8695) && !defined(KS8695X) */
/*
* SWITCH Engine registers bit difinitions
*/
#define KS8695_SEC0_BACKOFF_EN 0x80000000 /* new backoff enable for UNH, bit 31 */
#define KS8695_SEC0_NUH_MODE 0x00200000 /* NUH Mode, bit 21 */
#define KS8695_SEC0_PASS_ALL_FRAMES 0x00080000 /* pass all frames, bit 19 */
#define KS8695_SEC0_FRAME_LEN_CHECK 0x00020000 /* frame length field check, bit 17 */
#define KS8695_SEC0_DMA_HALF_DUPLEX 0x00000010 /* LAN DMA port 5 half duplex mode bit 4 */
#define KS8695_SWITCH_CTRL0_PASS_ALL_FRAMES KS8695_SEC0_PASS_ALL_FRAMES
#define KS8695_SEC1_NO_IEEE_AN 0x00000800 /* non IEEE specific auto-nego bit 11 */
#define KS8695_SEC1_TPID_MODE 0x00000400 /* Special TPID mode bit 10 */
#define KS8695_SEC1_NO_TX_8021X_FLOW_CTRL 0x00000080 /* IEEE 802.1x transmit flow control disable bit 7 */
#define KS8695_SEC1_NO_RX_8021X_FLOW_CTRL 0x00000040 /* IEEE 802.1x receive flow control disable bit 6 */
#define KS8695_SEC1_HUGE_PACKET 0x00000020 /* huge packet support bit 5 */
#define KS8695_SEC1_8021Q_VLAN_EN 0x00000010 /* IEEE 802.1q VLAN enable bit 4 */
#define KS8695_SEC1_MII_10BT 0x00000002 /* Switch MII 10BT bit 1 */
#define KS8695_SEC1_NULL_VID 0x00000001 /* null VID replacement bit 0 */
/* Port 1-4 and 5 Configuration Register Set 2 bit definition */
#define KS8695_SEPC2_VLAN_FILTER 0x10000000 /* Ingress VLAN filtering bit 28 */
#define KS8695_SEPC2_DISCARD_NON_PVID 0x08000000 /* discard non PVID packets, bit 27 */
#define KS8695_SEPC2_FORCE_FLOW_CTRL 0x04000000 /* force flow control, bit 26 */
#define KS8695_SEPC2_BACK_PRESSURE_EN 0x02000000 /* back pressure enable, bit 25 */
#define KS8695_SEPC2_TX_H_RATECTRL_MASK 0x00FFF000 /* Tx high priority rate control bit 23:12 */
#define KS8695_SEPC2_TX_L_RATECTRL_MASK 0x00000FFF /* Tx low priority rate control bit 11:0 */
/* Port 1-4 and 5 Configuration Register Set 3 bit definition */
#define KS8695_SEPC3_RX_H_RATECTRL_MASK 0xFFF00000 /* Rx high priority rate control bit 31:20 */
#define KS8695_SEPC3_RX_L_RATECTRL_MASK 0x000FFF00 /* Rx low priority rate control bit 19:8 */
#define KS8695_SEPC3_RX_DIF_RATECTRL_EN 0x00000080 /* Rx differential priority rate control enable bit 7 */
#define KS8695_SEPC3_RX_L_RATECTRL_EN 0x00000040 /* Rx low priority rate control enable bit 6 */
#define KS8695_SEPC3_RX_H_RATECTRL_EN 0x00000020 /* Rx high priority rate control enable bit 5 */
#define KS8695_SEPC3_RX_L_RATEFLOW_EN 0x00000010 /* Rx low priority rate flow control enable bit 4 */
#define KS8695_SEPC3_RX_H_RATEFLOW_EN 0x00000008 /* Rx high priority rate flow control enable bit 3 */
#define KS8695_SEPC3_TX_DIF_RATECTRL_EN 0x00000004 /* Tx low priority rate control enable bit 2 */
#define KS8695_SEPC3_TX_L_RATECTRL_EN 0x00000002 /* Tx low priority rate control enable bit 1 */
#define KS8695_SEPC3_TX_H_RATECTRL_EN 0x00000001 /* Tx high priority rate control enable bit 0 */
/* Indirect Access Control register bit definition */
#define KS8695_SEIAC_READ 0x00001000 /* bit 12 */
#define KS8695_SEIAC_WRITE 0x00000000 /* bit 12 not set*/
/* table select bit 11:10 */
#define KS8695_SEIAC_TAB_STATIC 0x00000000
#define KS8695_SEIAC_TAB_VLAN 0x00000400
#define KS8695_SEIAC_TAB_DYNAMIC 0x00000800
#define KS8695_SEIAC_TAB_MIB 0x00000C00
#define KS8695_SEIAC_INDEX_MASK 0x000003FF /* bit 9:0 */
/* LAN PHY power management related registers bit definition */
#define KS8695_LPPM_PHY_LOOPBACK 0x4000 /* phy loopback bit 14 */
#define KS8695_LPPM_RMT_LOOPBACK 0x2000 /* remote loopback bit 13 */
#define KS8695_LPPM_PHY_ISOLATE 0x1000 /* phy isolate bit 12 */
#define KS8695_LPPM_SOFT_RESET 0x0800 /* phy isolate bit 11 */
#define KS8695_LPPM_FORCE_LINK 0x0400 /* force link isolationi bit 10 */
/* WAN PHY Power mangement register bit definition */
#define KS8695_WPPM_PHY_LOOPBACK 0x00004000 /* phy loopback bit 14 */
#define KS8695_WPPM_RMT_LOOPBACK 0x00002000 /* remote loopback bit 13 */
#define KS8695_WPPM_PHY_ISOLATION 0x00001000 /* phy isolationi bit 12 */
#define KS8695_WPPM_FORCE_LINK 0x00000400 /* force link isolationi bit 10 */
/* PCI bit definition */
#define PCI_BMEM_PREFETCH 0x8
#define PCI_BMEM_PREFLMIT4 0x00000000
#define PCI_BMEM_PREFLMIT8 0x10000000
#define PCI_BMEM_PREFLMIT16 0x20000000
#define PCI_CONF_DISEXT 0x10000000
#define PCI_PCI_MODE 0x00000000
#define PCI_MINIPCI_MODE 0x20000000
#define PCI_CARDBUS_MODE 0x40000000
#define PCI_ENABLE_ADDTRAN 0x80000000
#ifndef TRUE
#define TURE 1
#define FALSE 0
#endif
#define PCI_REGINDEX_IDS (0 << 2)
#define PCI_REGINDEX_STCMD (1 << 2)
#define PCI_REGINDEX_REV (2 << 2)
#define PCI_REGINDEX_HEAD (3 << 2)
#define PCI_REGINDEX_BASE (4 << 2)
#define PCI_REGINDEX_SUBIDS (11 << 2)
#define PCI_REGINDEX_ROMBASE (12 << 2)
#define PCI_REGINDEX_INT (15 << 2)
#define PCI_BRIDGE_CLASS 0x6
#define PCI_TO_PCIBRIDGE 0x4
#define PCI_MAX_SLOT 8
#define PCI_NOTEXIST 0xFFFF
#define PCI_SUBSYSTEMID 0x86950000
#define PCI_SUBVENDORID 0x10
/* other parameters to set up FLASH/ROM/SRAM configuration registers */
#define ROM_BANK_ACCTM2 0x0
#define ROM_BANK_ACCTM3 (0x1 << 4)
#define ROM_BANK_ACCTM4 (0x2 << 4)
#define ROM_BANK_ACCTM5 (0x3 << 4)
#define ROM_BANK_ACCTM6 (0x4 << 4)
#define ROM_BANK_ACCTM7 (0x5 << 4)
#define ROM_BANK_ACCTM8 (0x6 << 4)
#define ROM_BANK_ACCTM9 (0x7 << 4)
#define ROM_BANK_PACTM2 0x0
#define ROM_BANK_PACTM3 (0x1 << 2)
#define ROM_BANK_PACTM4 (0x2 << 2)
#define ROM_BANK_PACTM5 (0x3 << 2)
#define ROM_BANK_PMOD0 0x0
#define ROM_BANK_PMOD1 0x1
#define ROM_BANK_PMOD2 0x2
#define ROM_BANK_PMOD3 0x3
#define ROM_GENERAL_SETTING 0x00000001
/* SDRAM banks */
#define SDRAM_NOP_COMD 0x30000
#define SDRAM_PRECHARGE_CMD 0x10000
#define SDRAM_REFRESH_TIMER 360
#define SDRAM_MODE_COMD 0x20033
#define SDRAM_RASCAS 0x0000000A
#define SDRAM_BANK_COLAB8 0x0
#define SDRAM_BANK_COLAB9 (0x1 << 8)
#define SDRAM_BANK_COLAB10 (0x2 << 8)
#define SDRAM_BANK_COLAB11 (0x3 << 8)
#define SDRAM_UNM_BANKS2 0x0
#define SDRAM_UNM_BANKS4 (0x1 << 3)
#define SDRAM_BANKS_DBW0 0x0
#define SDRAM_BANKS_DBW8 (0x1 << 1)
#define SDRAM_BANKS_DBW16 (0x2 << 1)
#define SDRAM_BANKS_DBW32 (0x3 << 1)
#define FLASH_BANK 0x00000000
#define FLASH_BANK_SIZE 0x00400000
#define SDRAM_BANK0_SIZE 0x01000000
#if !defined(KS8695) && !defined(KS8695X)
#define SDRAM_BANK1_SIZE 0x01000000 /* KS8695P has two SDRAM of 32M */
#else
#define SDRAM_BANK1_SIZE 0x00000000 /* KS8695/X has only one SDRAM of 16M */
#endif /* #if defined(KS8695) || defined(KS8695X) */
#define SDRAM_TOTAL_SIZE (SDRAM_BANK0_SIZE + SDRAM_BANK1_SIZE)
#define REMAPPED_FLASH_BANK 0x02800000 /* at 40MB */
#define SDRAM_BANK_0 FLASH_BANK_SIZE
#define SDRAM_BANK_1 (SDRAM_BANK_0 + SDRAM_BANK0_SIZE)
#define SDRAM_BANK_END (SDRAM_BANK_1 + SDRAM_BANK1_SIZE)
#define REMAPPED_SDRAM_BANK_0 0x0
#define REMAPPED_SDRAM_BANK_1 (REMAPPED_SDRAM_BANK_0 + SDRAM_BANK0_SIZE)
#define REMAPPED_SDRAM_BANK_END (REMAPPED_SDRAM_BANK_1 + SDRAM_BANK1_SIZE)
#define TMP_SDRAM_REG0 (((SDRAM_BANK_0+SDRAM_BANK0_SIZE-1)>>16)<<22)|((SDRAM_BANK_0>>16)<<12)|SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32
#define TMP_SDRAM_REG1 (((SDRAM_BANK_1+SDRAM_BANK1_SIZE-1)>>16)<<22)|((SDRAM_BANK_1>>16)<<12)|SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32
#define FLASH_ROM_START REMAPPED_FLASH_BANK
#define SDRAM_START SDRAM_BANK_0
#define RAM_LIMIT REMAPPED_SDRAM_BANK_END
#define ABT_STACK RAM_LIMIT
#define UNDEF_STACK ABT_STACK - 1024
#define SVC_STACK UNDEF_STACK - 1024
#define IRQ_STACK SVC_STACK - 2048
#define FIQ_STACK IRQ_STACK - 4096
#define SYS_STACK FIQ_STACK - 4096
#define USR_STACK SYS_STACK - 4096
#define RAM_LIMIT_TMP SDRAM_BANK_END - 2048
/* External I/O banks difintions */
#define EXT_IO_BANK_SIZE 0x00400000 /* 4MB */
#define EXT_IO_BANK_0 0x03200000 /* 50MB */
#define EXT_IO_BANK_1 (EXT_IO_BANK_0 + EXT_IO_BANK_SIZE) /* 54 MB */
#define EXT_IO_BANK_2 (EXT_IO_BANK_1 + EXT_IO_BANK_SIZE) /* 58 MB */
#define EXT_IOBANK_CLOCK0 0x0
#define EXT_IOBANK_CLOCK1 0x1
#define EXT_IOBANK_CLOCK2 0x2
#define EXT_IOBANK_CLOCK3 0x3
#define EXT_IOBANK_CLOCK4 0x4
#define EXT_IOBANK_CLOCK5 0x5
#define EXT_IOBANK_CLOCK6 0x6
#define EXT_IOBANK_CLOCK7 0x7
#define FLASH_REG (((FLASH_BANK+FLASH_BANK_SIZE-1)>>16)<<22)|((FLASH_BANK>>16)<<12)|ROM_BANK_PMOD0|ROM_BANK_ACCTM9
#define REM_FLASH_REG (((REMAPPED_FLASH_BANK+FLASH_BANK_SIZE-1)>>16)<<22)|((REMAPPED_FLASH_BANK>>16)<<12)|ROM_BANK_PMOD0|ROM_BANK_ACCTM9
#define REM_SDRAM_REG0 (((REMAPPED_SDRAM_BANK_0+SDRAM_BANK0_SIZE-1)>>16)<<22)|((REMAPPED_SDRAM_BANK_0>>16)<<12)|SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32
#define REM_SDRAM_REG1 (((REMAPPED_SDRAM_BANK_1+SDRAM_BANK1_SIZE-1)>>16)<<22)|((REMAPPED_SDRAM_BANK_1>>16)<<12)|SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32
#define EXTIO_REG0 (((EXT_IO_BANK_0+EXT_IO_BANK_SIZE-1)>>16)<<22)|((EXT_IO_BANK_0>>16)<<12)|(EXT_IOBANK_CLOCK1<<3)
#define EXTIO_REG1 (((EXT_IO_BANK_1+EXT_IO_BANK_SIZE-1)>>16)<<22)|((EXT_IO_BANK_1>>16)<<12)|(EXT_IOBANK_CLOCK1<<3)
#define EXTIO_REG2 (((EXT_IO_BANK_2+EXT_IO_BANK_SIZE-1)>>16)<<22)|((EXT_IO_BANK_2>>16)<<12)|(EXT_IOBANK_CLOCK1<<3)
/* GPIO configure defaults */
#define INIT_GPIO_MODE 0xFFFF
#define INIT_GPIO_DATA 0
#define INIT_GPIO_CTRL 0
#define INIT_INT 0
/* definitions for the AMBA UART */
#define N_KS8695P_UART_CHANNELS 1 /* number of KS8695P UART chans */
#define N_SIO_CHANNELS N_KS8695P_UART_CHANNELS
#define N_UART_CHANNELS N_KS8695P_UART_CHANNELS
#define UART_0_BASE_ADR REG_IO_BASE /* UART 0 base address */
#define KS8695P_REG(reg) \
(*(volatile UINT32 *)((UINT32)REG_IO_BASE + (reg)))
#define KS8695P_REG_READ(reg, result) \
(result) = (KS8695P_REG(reg))
#define KS8695P_REG_WRITE(reg, data) \
(KS8695P_REG(reg)) = (data)
#define KS8695P_REG_BIT_SET(reg, data) \
(KS8695P_REG(reg)) |= (data)
#define KS8695P_REG_BIT_CLR(reg, data) \
(KS8695P_REG(reg)) &= ~(data)
#if defined(KS8695) || defined(KS8695X) /* KS8695/X only */
#define KS8695_REG_READ KS8695P_REG_READ
#define KS8695_REG_WRITE KS8695P_REG_WRITE
#define KS8695_REG_BIT_SET KS8695P_REG_BIT_SET
#define KS8695_REG_BIT_CLR KS8695P_REG_BIT_CLR
#endif /* #if defined(KS8695) || defined(KS8695X) */
#define KS8695P_SYSCLK SYS_TIMER_CLK /* System bus clock */
#ifdef __cplusplus
}
#endif
#endif /* INCks8695p */
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