mc68hc908ql4.c

摩托罗拉公司发布的QL4的Lin总线kit,freescale网站上花钱买的

/*
** ###################################################################
**
**	MODIFIED FOR APP NOTE ON MC68HC908QL4 - NOT THE OFFICIAL BEAN MODULE
**     Filename  : MC68HC908QL4.C
**     Processor : MC68HC908QL4CP
**     Version   : Driver 00.01
**     Compiler  : Metrowerks HC08 C Compiler V-5.0.13
**     Date      :  8 Aug 2003
**     Author	 : Matt Ruff
**  Based on QY4 header file (info below)
**
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**
**     Filename  : M68HC908QY4.C
**
**     Processor : MC68HC908QY4CP
**
**     Version   : Driver 01.02
**
**     Compiler  : Metrowerks HC08 C Compiler V-5.0.13
**
**     Date/Time : 05.08.2002, 06:24
**
**     Abstract  :
**
**         This implements an IO devices mapping.
**
**     Settings  :
**
**
**
**     Contents  :
**
**         No public methods
**
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2002
**
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**
**     http      : www.processorexpert.com
**     mail      : [e-mail]
**
** ###################################################################
*/
/* Based on CPU DB MC68HC908QY4_P_DW, version 2.87.063 */
//#include <MC68HC908QY4.h>

#include "MC68HC908QL4.h"

volatile ADCLKSTR _ADCLK;        /* ADC Input Clock Register -MBR */
volatile ADRHSTR _ADRH;          /* ADC Data Register High   -MBR */
volatile ADRLSTR _ADRL;          /* ADC Data Register Low    -MBR */
volatile ADSCRSTR _ADSCR;      /* ADC Status and Control Register */
volatile BFCRSTR _BFCR;        /* SIM Break Flag Control Register */
volatile BRKARSTR _BRKAR;      /* Break Auxiliary Register */
volatile BRKHSTR _BRKH;        /* Break Address Register High */
volatile BRKLSTR _BRKL;        /* Break Address Register Low */
volatile BRKSCRSTR _BRKSCR;    /* Break Status and Control Register */
volatile CONFIG1STR _CONFIG1;  /* Configuration Register 1 */
volatile CONFIG2STR _CONFIG2;  /* Configuration Register 2 */
volatile COPCTLSTR _COPCTL;    /* COP Control Register */
volatile DDRASTR _DDRA;        /* Data Direction Register A */
volatile DDRBSTR _DDRB;        /* Data Direction Register B */
volatile FLBPRSTR _FLBPR;      /* FLASH Block Protect Register */
volatile FLCRSTR _FLCR;        /* FLASH Control Register */
volatile INT1STR _INT1;        /* Interrupt Statuts Register 1 */
volatile INT2STR _INT2;        /* Interrupt Statuts Register 2 */
volatile INT3STR _INT3;        /* Interrupt Statuts Register 3 */
volatile INTSCRSTR _INTSCR;    /* IRQ Status and Control Register */
volatile KBIERSTR _KBIER;      /* Keyboard Interrrupt Enable Register KBIER */
volatile KBSCRSTR _KBSCR;      /* Keyboard Status and Control Register */
volatile LVISRSTR _LVISR;      /* LVI Status Register */
volatile OptionalSTR _Optional; /* Internal Oscillator Trim */
volatile OSCSTATSTR _OSCSTAT;  /* Oscillator Status Register */
volatile OSCTRIMSTR _OSCTRIM;  /* Oscillator Trim Register */
volatile PTASTR _PTA;          /* Port A Data Register */
volatile PTAPUESTR _PTAPUE;    /* Input Pull-Up Enable Register PTAPUE */
volatile PTBSTR _PTB;          /* Port B Data Register */
volatile PTBPUESTR _PTBPUE;    /* Input Pull-Up Enable Register PTBPUE */
volatile BSRSTR _BSR;            /* Break Status Register     -MBR */
volatile SLCC1STR _SLCC1;
volatile SLCC2STR _SLCC2;
volatile SLCSSTR _SLCS;
volatile SLCPSTR _SLCP;
volatile SLCBTHSTR _SLCBTH;
volatile SLCBTLSTR _SLCBTL;
volatile SLCSVSTR _SLCSV;
volatile SLCDLCSTR _SLCDLC;
volatile SLCDSTR _SLCID;
volatile SLCDSTR _SLCD7;
volatile SLCDSTR _SLCD6;
volatile SLCDSTR _SLCD5;
volatile SLCDSTR _SLCD4;
volatile SLCDSTR _SLCD3;
volatile SLCDSTR _SLCD2;
volatile SLCDSTR _SLCD1;
volatile SLCDSTR _SLCD0;
volatile SRSRSTR _SRSR;        /* SIM Reset Status Register */
volatile TCNTHSTR _TCNTH;      /* TIM Counter Register Low */
volatile TCNTLSTR _TCNTL;      /* TIM Counter Register Low */
volatile TCH0HSTR _TCH0H;      /* TIM Channel 0 Register High */
volatile TCH0LSTR _TCH0L;      /* TIM Channel 0 Register Low */
volatile TCH1HSTR _TCH1H;      /* TIM Channel 1 Register High */
volatile TCH1LSTR _TCH1L;      /* TIM Channel 1 Register Low */
volatile TMODHSTR _TMODH;      /* TIM Counter Modulo Register High */
volatile TMODLSTR _TMODL;      /* TIM Counter Modulo Register Low */
volatile TSCSTR _TSC;          /* TIM Status and Control Register TSC */
volatile TSC0STR _TSC0;        /* TIM Channel 0 Status and Control Register */
volatile TSC1STR _TSC1;        /* TIM Channel 1 Status and Control Register */
volatile BRKSTR _BRK;          /* Break Address Register */
volatile TCNTSTR _TCNT;        /* TIM Counter Register */
volatile TCH0STR _TCH0;        /* TIM Channel 0 Register */
volatile TCH1STR _TCH1;        /* TIM Channel 1 Register */
volatile TMODSTR _TMOD;        /* TIM Counter Modulo Register */
/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 02.90 for 
**     the Motorola HC08 series of microcontrollers.
**
** ###################################################################
*/