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<title>Verilog HDL On-line Quick Reference Table of Contents</title>
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<font color="#FF0000" size=+1><b>Verilog HDL<br>
Quick Reference Guide</b></font><br>
<font size="-1" color="#FF0000">based on the IEEE 1364-1995 standard</font>
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<font size="-1"><b>by Sutherland HDL, Inc.</b></font><br>
<font size="-1" color="#FF0000"><i><b>Verilog Training Experts</b></i></font><br>
<font size="-1"><a href="http://www.sutherland-hdl.com" target="_top">
www.sutherland-hdl.com</a></font>
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<p align="center"><font color="#FF0000" face="Times New Roman" size=-1>copyright 1997, All
rights reserved.</font><br>
<font size="1">You <font color="#FF0000"><i><b>may</b></i></font> download this page for
personal use.<br>
You <font color="#FF0000"><i><b>may not</b></i></font> reproduce this document or any
portion thereof in any form! Verilog is a registered trademark of Cadence Design Systems,
San Jose, CA. </font></p>
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<a href="verilog_ref_guide.zip">download this guide as a zip file</a></br>
<a href="verilog_ref_guide.tar">download this guide as a tar file</a></font></p>
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<p align="center"><font size="3"><b>Table of Contents</b></font></p>
<p align="left"><a href="vlog_ref_body.html#1.0 Hierarchy Scopes">1.0 Hierarchy Scopes</a><br>
<a href="vlog_ref_body.html#2.0 Concurrency">2.0 Concurrency</a><br>
<a href="vlog_ref_body.html#3.0 Reserved Keywords">3.0 Reserved Keywords</a><br>
<a href="vlog_ref_body.html#4.0 Lexical Conventions">4.0 Lexical Conventions</a><br>
<a href="vlog_ref_body.html#5.0 Module Definitions">5.0 Module Definitions</a><br>
<a href="vlog_ref_body.html#6.0 Module Port Declarations">6.0 Module Port Declarations</a><br>
<a href="vlog_ref_body.html#7.0 Data Type Declarations">7.0 Data Type Declarations</a><br>
<a href="vlog_ref_body.html#7.1 Register Data Types">7.1 Register Data
Types</a><br>
<a href="vlog_ref_body.html#7.2 Net Data Types">7.2 Net Data Types</a><br>
<a href="vlog_ref_body.html#7.3 Other Data Types">7.3 Other Data Types</a><br>
<a href="vlog_ref_body.html#8.0 Module Instances">8.0 Module Instances</a><br>
<a href="vlog_ref_body.html#9.0 Primitive Instances">9.0 Primitive Instances</a><br>
<a href="vlog_ref_body.html#10.0 Procedural Blocks">10.0 Procedural Blocks</a><br>
<a href="vlog_ref_body.html#10.1 Timing Controls">10.1 Timing Controls</a><br>
<a href="vlog_ref_body.html#10.2 Procedural Assignments">10.2 Procedural
Assignments</a><br>
<a href="vlog_ref_body.html#10.3 Programming Statements">10.3
Programming Statements</a><br>
<a href="vlog_ref_body.html#11.0 Operators">11.0 Operators</a><br>
<a href="vlog_ref_body.html#12.0 Continuous Assignments">12.0 Continuous Assignments</a><br>
<a href="vlog_ref_body.html#13.0 Task Definitions">13.0 Task Definitions</a><br>
<a href="vlog_ref_body.html#14.0 Function Definitions">14.0 Function Definitions</a><br>
<a href="vlog_ref_body.html#15.0 Specify Blocks">15.0 Specify Blocks</a><br>
<a href="vlog_ref_body.html#16.0 User Defined Primitives (UDPs)">16.0 User Defined
Primitives</a><br>
<a href="vlog_ref_body.html#17.0 Synthesis Supported Constructs">17.0 Synthesis Constructs</a><br>
<a href="vlog_ref_body.html#18.0 System Tasks and Functions">18.0 System Tasks and
Functions</a><br>
<a href="vlog_ref_body.html#19.0 Compiler Directives">19.0 Compiler Directives</a> </p>
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