initial.asm

源程序是在VisualDSP环境下开发出来的

#include "def21160.h"           // Memory Mapped IOP register definitions 
#include "hddamacros.h"
.global   init;
// program memory code 
.section/pm seg_pmco;   
    
init:		ustat1=0x00020084; //wait register setting
			DM(WAIT)=ustat1;
			USTAT2=0x08000;
			dm(SYSCON)=USTAT2;
			mode2=0x78000;
			bit set mode2 FLG0|FLG1|FLG2|FLG3;
 			bit set FLAGS FLG3;
			call delay100;
			call delay100; 			
			bit clr FLAGS FLG3;
			bit set FLAGS FLG3;
			bit clr FLAGS FLG0;

//initial PCF8584			
			
			bit set FLAGS FLG2;
			nop;


/*************from here is pcf8584 initial program;*******************************/
			px1=0x0;//load 80h into REG S1,serial interface off
			px2=0x00800000;
			call s1write;

			px2=0x00550000;//load own effective address,shifted into AAh s0'
            call othregwr;

			px2=0x00100000;//load byte 10 into REG S1,next byte will be read from......  		
			call s1write;  //...interrupt vector REG S3
    		
			px2=0x00ab0000;//write into S3,in order to make the value of s2 is correct.
            call othregwr;

			px2=0x00a00000;//load byte 20 into REG S1,next byte will be loaded into......  		
			call s1write;  //...clock control REG S2

			px2=0x00010000;//system clock is 3MHz,scl clock is 1.5KHz
			call othregwr;

			px2=0x00c10000;//loads byte C1H into S1,enable serial interface,
			call s1write;  //set iic-bus into idle mode


/*************initialization of PCF8584 completed;**************************/

/*************from here is KS0127 initialzation**************************/
//busbusy:	call s1read;   //read from S1 register;
//			r0=px2;
//			btst r0 by 16;
//			if sz jump busbusy; //BB bit--bus busy,then waiting
//write to DMDA register--index value is 0x01
			px2=0x00d80000;//send 0127 slave address,data transfer is write into iic bus
			call othregwr;

			px2=0x00c50000;//load c5 into s1,pcf8584 generates the 'START' condition 
			call s1write;//and clocks out the slave address and the clock pulse for slave
			             //acknowledgement.Next byte sent to s0 reg will be transferred over the iic bus

//0127 index address--0127  reg index value--the reg you write
			px2=0x00010000;
			call othregwr;
#ifdef	NTSC
//NTSC的情况
			px2=0x002c0000;		
			call othregwr;
#else
//PAL的情况
			px2=0x002e0000;		
			call othregwr;
#endif			

notover:	call s1read;//read from s1,Poll for transmission finished.
			r0=px2;
			btst r0 by 23;
			if not sz jump notover;//PIN bit=1,data transmission not over waiting
			btst r0 by 19;// slave acknowledged?if not jump transvover;
			if sz jump transmitov;
			nop;

transmitov:	px2=0x00c30000;//Load c3 into the s1,8584 generateds 'STOP' condition.
			call s1write;
//////////////////////////////////////////////////////////////////
//write to CMDB--index value is 1e
			px2=0x00d80000;//send 0127 slave address,data transfer is write into iic bus
			call othregwr;

			px2=0x00c50000;//load c5 into s1,pcf8584 generates the 'START' condition 
			call s1write;//and clocks out the slave address and the clock pulse for slave
			             //acknowledgement.Next byte sent to s0 reg will be transferred over the iic bus

//0127 index address--0127  reg index value--the reg you write
			px2=0x00020000;
			call othregwr;
			
			r0=0x20;
			r4=r4 or r0;
			r4=lshift r4 by 16;
			px2=r4;		
//			px2=0x00210000;		
			call othregwr;

			px2=0x00c30000;//Load c3 into the s1,8584 generateds 'STOP' condition.
			call s1write;
 
//write to OFMTA--index value is 1e
			px2=0x00d80000;//send 0127 slave address,data transfer is write into iic bus
			call othregwr;

			px2=0x00c50000;//load c5 into s1,pcf8584 generates the 'START' condition 
			call s1write;//and clocks out the slave address and the clock pulse for slave
			             //acknowledgement.Next byte sent to s0 reg will be transferred over the iic bus

//0127 index address--0127  reg index value--the reg you write
			px2=0x001e0000;
			call othregwr;
			
			px2=0x00150000;		
			call othregwr;

			px2=0x00c30000;//Load c3 into the s1,8584 generateds 'STOP' condition.
			call s1write;

//write to REFCOD--index value is 0x31
			px2=0x00d80000;//send 0127 slave address,data transfer is write into iic bus
			call othregwr;

			px2=0x00c50000;//load c5 into s1,pcf8584 generates the 'START' condition 
			call s1write;//and clocks out the slave address and the clock pulse for slave
			             //acknowledgement.Next byte sent to s0 reg will be transferred over the iic bus

//0127 index address--0127  reg index value--the reg you write
			px2=0x00310000;
			call othregwr;
			
			px2=0x00000000;	//the REFCOD value	
			call othregwr;

			px2=0x00c30000;//Load c3 into the s1,8584 generateds 'STOP' condition.
			call s1write;




/************* KS0127 initialzation  over **************************/


//************next is master receive,read one byte from 0127 *//
			px2=0x00d80000;//send 0123 slave address,r/w=0,data transfer is write into iic bus
			call othregwr;

			px2=0x00c50000;//load c5 into s1,pcf8584 generates the 'START' condition 
			call s1write;//and clocks out the slave address and the clock pulse for slave
			             //acknowledgement.Next byte sent to s0 reg will be transferred over the iic bus
//0127 index address--control reg index value--the reg you want read
			px2=0x00020000;
			call othregwr;

			
			px2=0x00c30000;//Load c3 into the s1,8584 generateds 'STOP' condition.
			call s1write;

			
			px2=0x00d90000;//send 0127 slave address,r/w=1,data transfer is read from iic bus
			call othregwr;

			px2=0x00c50000;//load c5 into s1,pcf8584 generates the 'START' condition 
			call s1write;//and clocks out the slave address adn the clock pulse for slave
			             //acknowledgement.Next byte sent to s0 reg will be transferred over the iic bus


			px2=0x00400000;//Set ACK bit s1 to 0 in preparation for negative acknowledgement.
			call s1write;

			call othregrd;
			call s1read;

			px2=0x00c30000;
			call s1write;

			call othregrd;
			rts;
//************ master receive over ,pcf8584 has read one byte from 0127,load in px2 *//
		
s1write:    r1=22;
			bit clr FLAGS FLG2;			
			lcntr=r1,do loop1 until lce;
loop1:		dm(0xc00001)=px;
			bit set FLAGS FLG2;
			call delay100;
			rts;

othregwr:	r1=22;
			bit clr FLAGS FLG2;
			lcntr=r1,do loop2 until lce;
loop2:		dm(0xc00000)=px;
			bit set FLAGS FLG2;
			call delay100;//while consecutive access to pcf8584,wait for 100 clock
			rts;

s1read:     r1=22;
            bit clr FLAGS FLG2;
			lcntr=r1,do loop3 until lce;
loop3:		px=dm(0xd00001);
			bit set FLAGS FLG2;
			call delay100;//while consecutive access to pcf8584,wait for 100 clock
			rts;

othregrd:	r1=22;	
			bit clr FLAGS FLG2;
			lcntr=r1,do loop4 until lce;
loop4:		px=dm(0xd00000);
			bit set FLAGS FLG2;
			call delay100;	
			rts;

delay100:	r0=20000;   
			lcntr=r0, do loop100 until lce;
loop100:	nop;
			rts;
init.end: