codec_a_in_test.c

源程序是在VisualDSP环境下开发出来的

/* File: codec_a_in_test.c  */
#include <defTS101.h>
#include <sysreg.h>
#include <builtins.h>
#include <signal.h>
#include <math.h> 
#include "TCB_A.h"

extern void boot_data(void);

extern void sysinit(void);
extern void i2c(void);

void dma0_int();
void irq0_int();
void frame_test();
void SetTCB0_trans(long DI_Source, long DX_Source, long DY_Source, long DP_Source,
             	   long DI_Destin, long DX_Destin, long DY_Destin, long DP_Destin);
void SetLink3TCB_trans(long DI,long DX,long DY,long DP);

int line_in_cnt;
//long tcb_di_temp;
int *Ptr_datain,*Ptr_dataout;
int sw_flag=0;

void main(void)
{
	volatile int temp;
	line_in_cnt = 0;
	Ptr_datain = data_a_buf1;
	Ptr_dataout = data_a_buf2;
//	tcb_di_temp = 0x4000000;
	sysinit();
	boot_data();
	
	i2c();
	// open int
	temp = __builtin_sysreg_read(__IMASKL);
    temp = temp | INT_DMA0;
    __builtin_sysreg_write(__IMASKL, temp);
    temp = __builtin_sysreg_read(__IMASKH);
    temp = temp | INT_GIE | INT_IRQ0;
    __builtin_sysreg_write(__IMASKH, temp);
    
    temp = LCTL_LREN | LCTL_PSIZE | LCTL_LTEN | LCTL_DIV8;
    __builtin_sysreg_write(__LCTL3, temp);
    
    //set int_table
    interruptf(SIGDMA0, dma0_int);
    interruptf(SIGIRQ0, irq0_int);
    
    Fifo2SdramSourceTCB.DP = (TCB_FLYBY | TCB_NORMAL | TCB_INT );
    Fifo2SdramDestinTCB.DP = (TCB_EXTMEM | TCB_NORMAL | TCB_INT);
	Link3TCB.DP = (TCB_EXTMEM | TCB_QUAD | TCB_DMAR);
	
	while(1);

}

//***********************************************************************
// Setup DMA TCB0 register (DI_Source, DX_Source, DY_Source, DP_Source
//                          DI_Destin, DX_Destin, DY_Destin, DP_Destin)
//***********************************************************************

void SetTCB0_trans(long DI_Source, long DX_Source, long DY_Source, long DP_Source,
            	   long DI_Destin, long DX_Destin, long DY_Destin, long DP_Destin)
{
    volatile __builtin_quad TCB_Clear, TCB_Set;

    TCB_Clear = __builtin_compose_128((long long)TCB_DISABLE << 32, 0);
    __builtin_sysreg_write4(__DCS0, TCB_Clear); 
    __builtin_sysreg_write4(__DCD0, TCB_Clear); 
    TCB_Set = __builtin_compose_128(((long long)DX_Source << 32) | DI_Source, ((long long)DP_Source << 32) | DY_Source);
    __builtin_sysreg_write4(__DCS0, TCB_Set); 
    TCB_Set = __builtin_compose_128(((long long)DX_Destin << 32) | DI_Destin, ((long long)DP_Destin << 32) | DY_Destin );
    __builtin_sysreg_write4(__DCD0, TCB_Set); 
}

void SetLink3TCB_trans(long DI,long DX,long DY,long DP)
{
	volatile __builtin_quad TCB_Clear, TCB_Set;
	TCB_Clear = __builtin_compose_128((long long)TCB_DISABLE << 32, 0);
	__builtin_sysreg_write4(__DC7, TCB_Clear);
	TCB_Set = __builtin_compose_128(((long long)DX << 32) | DI, ((long long)DP << 32) | DY);
	__builtin_sysreg_write4(__DC7, TCB_Set); 
}
	
//***********************************************************************

void irq0_int(void)
{
	if(fmod(sw_flag,2) ==0)
	{
		Ptr_datain = data_a_buf1;
		Ptr_dataout = data_a_buf2;
	}
	else
	{
		Ptr_datain = data_a_buf2;
		Ptr_dataout = data_a_buf1;
	}
	Fifo2SdramDestinTCB.DI = (long) Ptr_datain;
	Link3TCB.DI = (long) Ptr_dataout;
	
	SetTCB0_trans(Fifo2SdramSourceTCB.DI,Fifo2SdramSourceTCB.DX,Fifo2SdramSourceTCB.DY,Fifo2SdramSourceTCB.DP,
			   	  Fifo2SdramDestinTCB.DI,Fifo2SdramDestinTCB.DX,Fifo2SdramDestinTCB.DY,Fifo2SdramDestinTCB.DP);
	line_in_cnt++; 
	sw_flag++;
}

void dma0_int(void)
{
//	if(line_in_cnt == 525) frame_test();
//	tcb_di_temp = tcb_di_temp + 361;
//	Fifo2SdramDestinTCB.DI = tcb_di_temp ;
	
	SetLink3TCB_trans(Link3TCB.DI,Link3TCB.DX,Link3TCB.DY,Link3TCB.DP);			   		
}

void frame_test(void)
{
	int i;
	for(i=0;i<2;i++);
}