coder_d_out.c

源程序是在VisualDSP环境下开发出来的

#include <defTS101.h>
#include <sysreg.h>
#include <builtins.h>
#include <signal.h>
#include <math.h>
#include "TCB_D.h"

extern void sysinit(void);

void dma0_d_int();
//void irq0_d_int();
void link3_recv_int();
void frame_test();
void SetTCB0_trans(long DI_Source, long DX_Source, long DY_Source, long DP_Source,
             	   long DI_Destin, long DX_Destin, long DY_Destin, long DP_Destin);
void SetLink3TCB_recv(long DI,long DX,long DY,long DP);

int line_in_cnt,sqctl_reg;
//long tcb_di_temp;
long *Ptr_datain,*Ptr_dataout;
int sw_flag=0;

void main (void)
{
	volatile int temp;
	line_in_cnt = 0;
//	tcb_di_temp = 0x4000000;
	sysinit();
	
	sqctl_reg = __builtin_sysreg_read(__SQCTL);	
    sqctl_reg = sqctl_reg | 0x00F00000;
	sqctl_reg = sqctl_reg & 0xF0FFFFFF;
	__builtin_sysreg_write(__SQCTL, sqctl_reg);
    
	// open int
	temp = __builtin_sysreg_read(__IMASKL);
    temp = temp | INT_DMA0;
    __builtin_sysreg_write(__IMASKL, temp);
    temp = __builtin_sysreg_read(__IMASKH);
    temp = temp | INT_GIE | INT_DMA11;
    __builtin_sysreg_write(__IMASKH, temp);
    
    temp = LCTL_LREN | LCTL_PSIZE | LCTL_LTEN | LCTL_DIV8;
    __builtin_sysreg_write(__LCTL3, temp);
    
    //set int_table
    interruptf(SIGDMA0, dma0_d_int);
    interruptf(SIGDMA11, link3_recv_int);     
//    interruptf(SIGIRQ0, irq0_d_int);  
      
    Sdram2FifoSourceTCB.DP = (TCB_EXTMEM | TCB_NORMAL | TCB_INT );
    Sdram2FifoDestinTCB.DP = (TCB_FLYBY | TCB_NORMAL | TCB_INT);
    Link3TCB.DP = (TCB_EXTMEM | TCB_QUAD | TCB_DMAR | TCB_INT);		
	
    Sdram2FifoSourceTCB.DI = (long) data_d_buf2;
    Link3TCB.DI = (long) data_d_buf1;
    SetLink3TCB_recv(Link3TCB.DI,Link3TCB.DX,Link3TCB.DY,Link3TCB.DP);
    
	while(1);

}

//***********************************************************************
// Setup DMA TCB0 register (DI_Source, DX_Source, DY_Source, DP_Source
//                          DI_Destin, DX_Destin, DY_Destin, DP_Destin)
//***********************************************************************

void SetTCB0_trans(long DI_Source, long DX_Source, long DY_Source, long DP_Source,
            	   long DI_Destin, long DX_Destin, long DY_Destin, long DP_Destin)
{
    volatile __builtin_quad TCB_Clear, TCB_Set;

    TCB_Clear = __builtin_compose_128((long long)TCB_DISABLE << 32, 0);
    __builtin_sysreg_write4(__DCS0, TCB_Clear); 
    __builtin_sysreg_write4(__DCD0, TCB_Clear); 
    TCB_Set = __builtin_compose_128(((long long)DX_Source << 32) | DI_Source, ((long long)DP_Source << 32) | DY_Source);
    __builtin_sysreg_write4(__DCS0, TCB_Set); 
    TCB_Set = __builtin_compose_128(((long long)DX_Destin << 32) | DI_Destin, ((long long)DP_Destin << 32) | DY_Destin );
    __builtin_sysreg_write4(__DCD0, TCB_Set); 
}

void SetLink3TCB_recv(long DI,long DX,long DY,long DP)
{
	volatile __builtin_quad TCB_Clear, TCB_Set;
	TCB_Clear = __builtin_compose_128((long long)TCB_DISABLE << 32, 0);
	__builtin_sysreg_write4(__DC11, TCB_Clear);
	TCB_Set = __builtin_compose_128(((long long)DX << 32) | DI, ((long long)DP << 32) | DY);
	__builtin_sysreg_write4(__DC11, TCB_Set); 
}

/*
void irq0_d_int()
{
	SetTCB0_trans(Sdram2FifoSourceTCB.DI,Sdram2FifoSourceTCB.DX,Sdram2FifoSourceTCB.DY,Sdram2FifoSourceTCB.DP,
			   	  Sdram2FifoDestinTCB.DI,Sdram2FifoDestinTCB.DX,Sdram2FifoDestinTCB.DY,Sdram2FifoDestinTCB.DP);
	line_in_cnt++;
}
*/
void link3_recv_int()
{
	SetTCB0_trans(Sdram2FifoSourceTCB.DI,Sdram2FifoSourceTCB.DX,Sdram2FifoSourceTCB.DY,Sdram2FifoSourceTCB.DP,
			   	  Sdram2FifoDestinTCB.DI,Sdram2FifoDestinTCB.DX,Sdram2FifoDestinTCB.DY,Sdram2FifoDestinTCB.DP);
}

void dma0_d_int()
{
	sw_flag++;
	//set flag0---global flag
    sqctl_reg = sqctl_reg | 0x01000000;
    
	if(line_in_cnt <=620 && line_in_cnt >= 308)
		sqctl_reg = sqctl_reg & 0xFDFFFFFF;

	else
		sqctl_reg = sqctl_reg | 0x02000000;
		
	__builtin_sysreg_write(__SQCTL, sqctl_reg);
	
//	tcb_di_temp = tcb_di_temp + 360;
	
	if(line_in_cnt == 625) 
		{	
			line_in_cnt =0;
//			tcb_di_temp = 0x4000000;
		}
			
//	Sdram2FifoSourceTCB.DI = tcb_di_temp ;
    SetLink3TCB_recv(Link3TCB.DI,Link3TCB.DX,Link3TCB.DY,Link3TCB.DP);
	line_in_cnt++;
	
	if(fmod(sw_flag,2) ==0)
	{
		Ptr_datain = data_d_buf1;
		Ptr_dataout = data_d_buf2;
	}
	else
	{
		Ptr_datain = data_d_buf2;
		Ptr_dataout = data_d_buf1;
	}
	Sdram2FifoSourceTCB.DI = (long) Ptr_dataout;
	Link3TCB.DI = (long) Ptr_datain;
}

void frame_d_test()
{
	int i;
	for(i=0;i<2;i++);
}