md.texi

GCC

@item N
Exact power of 2

@item O
Zero

@item P
Constant whose negation is a signed 16-bit constant

@item G
Floating point constant that can be loaded into a register with one
instruction per word

@item Q
Memory operand that is an offset from a register (@samp{m} is preferable
for @code{asm} statements)

@item R
AIX TOC entry

@item S
Constant suitable as a 64-bit mask operand

@item T
Constant suitable as a 32-bit mask operand

@item U
System V Release 4 small data area reference
@end table

@item Intel 386---@file{i386.h}
@table @code
@item q
@samp{a}, @code{b}, @code{c}, or @code{d} register

@item A
Specifies the @samp{a} or @samp{d} registers.  This is primarily useful
for 64-bit integer values intended to be returned with the @samp{d}
register holding the most significant bits and the @samp{a} register
holding the least significant bits.

@item f
Floating point register

@item t
First (top of stack) floating point register

@item u
Second floating point register

@item a
@samp{a} register

@item b
@samp{b} register

@item c
@samp{c} register

@item d
@samp{d} register

@item D
@samp{di} register

@item S
@samp{si} register

@item I
Constant in range 0 to 31 (for 32-bit shifts)

@item J
Constant in range 0 to 63 (for 64-bit shifts)

@item K
@samp{0xff}

@item L
@samp{0xffff}

@item M
0, 1, 2, or 3 (shifts for @code{lea} instruction)

@item N
Constant in range 0 to 255 (for @code{out} instruction)

@item G
Standard 80387 floating point constant
@end table

@item Intel 960---@file{i960.h}
@table @code
@item f
Floating point register (@code{fp0} to @code{fp3})

@item l
Local register (@code{r0} to @code{r15})

@item b
Global register (@code{g0} to @code{g15})

@item d
Any local or global register

@item I
Integers from 0 to 31

@item J
0

@item K
Integers from @minus{}31 to 0

@item G
Floating point 0

@item H
Floating point 1
@end table

@item MIPS---@file{mips.h}
@table @code
@item d
General-purpose integer register

@item f
Floating-point register (if available)

@item h
@samp{Hi} register

@item l
@samp{Lo} register

@item x
@samp{Hi} or @samp{Lo} register

@item y
General-purpose integer register

@item z
Floating-point status register

@item I
Signed 16-bit constant (for arithmetic instructions)

@item J
Zero

@item K
Zero-extended 16-bit constant (for logic instructions)

@item L
Constant with low 16 bits zero (can be loaded with @code{lui})

@item M
32-bit constant which requires two instructions to load (a constant
which is not @samp{I}, @samp{K}, or @samp{L})

@item N
Negative 16-bit constant

@item O
Exact power of two

@item P
Positive 16-bit constant

@item G
Floating point zero

@item Q
Memory reference that can be loaded with more than one instruction
(@samp{m} is preferable for @code{asm} statements)

@item R
Memory reference that can be loaded with one instruction
(@samp{m} is preferable for @code{asm} statements)

@item S
Memory reference in external OSF/rose PIC format
(@samp{m} is preferable for @code{asm} statements)
@end table

@item Motorola 680x0---@file{m68k.h}
@table @code
@item a
Address register

@item d
Data register

@item f
68881 floating-point register, if available

@item x
Sun FPA (floating-point) register, if available

@item y
First 16 Sun FPA registers, if available

@item I
Integer in the range 1 to 8

@item J
16-bit signed number

@item K
Signed number whose magnitude is greater than 0x80

@item L
Integer in the range @minus{}8 to @minus{}1

@item M
Signed number whose magnitude is greater than 0x100

@item G
Floating point constant that is not a 68881 constant

@item H
Floating point constant that can be used by Sun FPA
@end table

@item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
@table @code
@item a
Register 'a'

@item b
Register 'b'

@item d
Register 'd'

@item q
An 8-bit register

@item t
Temporary soft register _.tmp

@item u
A soft register _.d1 to _.d31

@item w
Stack pointer register

@item x
Register 'x'

@item y
Register 'y'

@item z
Pseudo register 'z' (replaced by 'x' or 'y' at the end)

@item A
An address register: x, y or z

@item B
An address register: x or y

@item D
Register pair (x:d) to form a 32-bit value

@item L
Constants in the range @minus{}65536 to 65535

@item M
Constants whose 16-bit low part is zero

@item N
Constant integer 1 or @minus{}1

@item O
Constant integer 16

@item P
Constants in the range @minus{}8 to 2

@end table

@need 1000
@item SPARC---@file{sparc.h}
@table @code
@item f
Floating-point register that can hold 32- or 64-bit values.

@item e
Floating-point register that can hold 64- or 128-bit values.

@item I
Signed 13-bit constant

@item J
Zero

@item K
32-bit constant with the low 12 bits clear (a constant that can be
loaded with the @code{sethi} instruction)

@item G
Floating-point zero

@item H
Signed 13-bit constant, sign-extended to 32 or 64 bits

@item Q
Floating-point constant whose integral representation can
be moved into an integer register using a single sethi
instruction

@item R
Floating-point constant whose integral representation can
be moved into an integer register using a single mov
instruction

@item S
Floating-point constant whose integral representation can
be moved into an integer register using a high/lo_sum
instruction sequence

@item T
Memory address aligned to an 8-byte boundary

@item U
Even register

@end table

@item TMS320C3x/C4x---@file{c4x.h}
@table @code
@item a
Auxiliary (address) register (ar0-ar7)

@item b
Stack pointer register (sp)

@item c
Standard (32-bit) precision integer register

@item f
Extended (40-bit) precision register (r0-r11)

@item k
Block count register (bk)

@item q
Extended (40-bit) precision low register (r0-r7)

@item t
Extended (40-bit) precision register (r0-r1)

@item u
Extended (40-bit) precision register (r2-r3)

@item v
Repeat count register (rc)

@item x
Index register (ir0-ir1)

@item y
Status (condition code) register (st)

@item z
Data page register (dp)

@item G
Floating-point zero

@item H
Immediate 16-bit floating-point constant

@item I
Signed 16-bit constant