📄 main.c
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#include "ddsapi.h"
#include "table.h"
#include "exchange.h"
#include <stdlib.h>
#define SB(var, num) *(((BYTE*)&var)+num)
#define SIGN_BIT 0x08
#define QUATER_BIT 0x04
#define TABLE_MASK 0x03FF
#define FREQ_MULT 4295
#define INIT_FREQ 1000
#define MAX_FREQ 30000
extern volatile BOOL ready;
extern char rx_buffer[];
static DWORD accum = 0, dphase = INIT_FREQ*FREQ_MULT;
static WORD adr = 0;
static BYTE msb, lsb;
#pragma ioport DAC_MSB_CR0: 0x080
BYTE DAC_MSB_CR0;
#pragma ioport DAC_LSB_CR0: 0x090
BYTE DAC_LSB_CR0;
//you must change these values accordingly to your DAC9 placement,
//alternatively you can use the fixed version of the DAC_WriteStall2B()
void main()
{
DAC_Start(DAC_FULLPOWER);
PGA_FIL1_Start(PGA_FIL1_HIGHPOWER);
PGA_FIL2_Start(PGA_FIL2_HIGHPOWER);
PGA_OUT_Start(PGA_OUT_HIGHPOWER);
SPIS_Start(SPIS_LSB_FIRST);
PGA_FIL2_GAIN_CR1 |= 0x40;
PGA_FIL2_GAIN_CR2 &= ~0x40;
//enable comparator bus and disable the output latch
// but comparator bus is column clock synchronized still
OpenExchange();
M8C_EnableGInt;
ExchangeSend("The DDS generator is ready.\n\r");
while(1)
{
msb = strlen(rx_buffer)-2;
switch (rx_buffer[msb])
{
case 'f':
case 'F':
rx_buffer[msb] = 0;
dphase = FREQ_MULT*atof(rx_buffer);
ExchangeSend("The frequency was set well.\n\r");
break;
case 'g':
case 'G':
rx_buffer[msb] = 0;
lsb = atoi(rx_buffer);
if (lsb < GAIN_LEVELS)
{
PGA_OUT_SetGain(gain_table[lsb]);
ExchangeSend("The gain was set well.\n\r");
}
break;
default:
break;
}
ready = TRUE;
while(ready)
{
accum += dphase;
SB(adr,0) = SB(accum,0);
SB(adr,1) = SB(accum,1);
if (SB(accum,0) & QUATER_BIT) adr ^= 0xFFFF;
adr &= TABLE_MASK;
msb = lsb = sin_table[adr];
msb >>= 3;
msb |= 0x80;
lsb &= 0x07;
lsb <<= 2;
lsb |= 0x80;
if (SB(accum,0) & SIGN_BIT)
msb |= 0x20;
else
lsb |= 0x20;
M8C_Stall;
DAC_MSB_CR0 = msb;
M8C_Unstall;
DAC_LSB_CR0 = lsb;
//instead it, the fixed version DAC_WriteStall2B(lsb, msb) can be used
//but you have less time reserve
}
}
}
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