pga_fil1.h

用VC编辑的一个MD5算法

//************************************************************************
//************************************************************************
//
// PGA_FIL1.h for PGA_A
//
//  C declarations for the Continuous Time Programmable Gain Amplifier
// Copyright (c) 2000-2002 Cypress Microsystems, Inc. All rights reserved.
// Rev B, 2002 Mar 30
// UserModuleID "PGA_A" 
//
//************************************************************************
//************************************************************************
#include <M8C.h>

#define PGA_FIL1_OFF         0
#define PGA_FIL1_LOWPOWER    1
#define PGA_FIL1_MEDPOWER    2
#define PGA_FIL1_HIGHPOWER   3

#define PGA_FIL1_G16_0    0x08
#define PGA_FIL1_G8_00    0x18
#define PGA_FIL1_G5_33    0x28
#define PGA_FIL1_G4_00    0x38
#define PGA_FIL1_G3_20    0x48
#define PGA_FIL1_G2_67    0x58
#define PGA_FIL1_G2_27    0x68
#define PGA_FIL1_G2_00    0x78
#define PGA_FIL1_G1_78    0x88
#define PGA_FIL1_G1_60    0x98
#define PGA_FIL1_G1_46    0xA8
#define PGA_FIL1_G1_33    0xB8
#define PGA_FIL1_G1_23    0xC8
#define PGA_FIL1_G1_14    0xD8
#define PGA_FIL1_G1_06    0xE8
#define PGA_FIL1_G1_00    0xF8
#define PGA_FIL1_G0_93    0xE0
#define PGA_FIL1_G0_87    0xD0
#define PGA_FIL1_G0_81    0xC0
#define PGA_FIL1_G0_75    0xB0
#define PGA_FIL1_G0_68    0xA0
#define PGA_FIL1_G0_62    0x90
#define PGA_FIL1_G0_56    0x80
#define PGA_FIL1_G0_50    0x70
#define PGA_FIL1_G0_43    0x60
#define PGA_FIL1_G0_37    0x50
#define PGA_FIL1_G0_31    0x40
#define PGA_FIL1_G0_25    0x30
#define PGA_FIL1_G0_18    0x20
#define PGA_FIL1_G0_12    0x10
#define PGA_FIL1_G0_06    0x00



#pragma fastcall PGA_FIL1_Start
#pragma fastcall PGA_FIL1_SetPower

#pragma fastcall PGA_FIL1_SetGain

#pragma fastcall PGA_FIL1_Stop


extern void PGA_FIL1_Start(char power);
extern void PGA_FIL1_SetPower(char power);

extern void PGA_FIL1_SetGain(char chout);

extern void PGA_FIL1_Stop(void);


/************************************************
*  Hardware Register Definitions
*************************************************/
#pragma ioport  PGA_FIL1_GAIN_CR0:  0x075
BYTE            PGA_FIL1_GAIN_CR0;
#pragma ioport  PGA_FIL1_GAIN_CR1:  0x076
BYTE            PGA_FIL1_GAIN_CR1;
#pragma ioport  PGA_FIL1_GAIN_CR2:  0x077
BYTE            PGA_FIL1_GAIN_CR2;