spis.inc

来自「用VC编辑的一个MD5算法」· INC 代码 · 共 48 行

;------------------------------------------------------------------------------
;  FILENAME:   SPIS.inc
;   VERSION:    Rev B, 2002 Mar 30
;------------------------------------------------------------------------------
;  DESCRIPTION:
;     Assembler include file of SPIS instance of SPIS
;     user module.
;------------------------------------------------------------------------------
;	Copyright (c) Cypress MicroSystems 2000-2002. All Rights Reserved.
;------------------------------------------------------------------------------

;mask value for global int reg bit for TX instance
bSPIS_INT_MASK:             equ 40h  
;SPIS interrupt address
SPIS_INT_REG:               equ 0e1h  

;---------------------------------
; SPIS PSoC Block Registers
;---------------------------------
SPIS_CONTROL_REG:   equ 3bh                      ;Control register
SPIS_SHIFT_REG: equ 38h                          ;TX Shift Register register
SPIS_TX_BUFFER_REG: equ 39h                      ;TX Buffer Register
SPIS_RX_BUFFER_REG: equ 3ah                      ;RX Buffer Register
SPIS_FUNCTION_REG:  equ 38h                      ;Function register
SPIS_INPUT_REG: equ 39h                          ;Input register
SPIS_OUTPUT_REG:    equ 3ah                      ;Output register


;-------------------------------
; SPI Configuration definitions
;-------------------------------
SPIS_MODE_0:                  equ   00h      ;MODE 0 - Leading edge latches data - pos clock
SPIS_MODE_1:                  equ   02h      ;MODE 1 - Leading edge latches data - neg clock
SPIS_MODE_2:                  equ   04h      ;MODE 2 - Trailing edge latches data - pos clock
SPIS_MODE_3:                  equ   06h      ;MODE 3 - Trailing edge latches data - neg clock
SPIS_LSB_FIRST:               equ   80h      ;LSB bit transmitted/received first
SPIS_MSB_FIRST:               equ   00h      ;MSB bit transmitted/received first

;---------------------------
; SPI Status register masks
;---------------------------
SPIS_RX_OVERRUN_ERROR:        equ   40h      ;Overrun error in received data
SPIS_TX_BUFFER_EMPTY:         equ   10h      ;TX Buffer register is ready for next data byte
SPIS_RX_BUFFER_FULL:          equ   08h      ;RX Buffer register has received current data
SPIS_SPI_COMPLETE:            equ   20h      ;SPI Tx/Rx cycle has completed

; end of file