psocgpioint.h

来自「用VC编辑的一个MD5算法」· C头文件 代码 · 共 113 行

// AnalogColumn_InputMUX_1 address and mask defines
#pragma	ioport	AnalogColumn_InputMUX_1_Bypass_ADDR:	0x2
BYTE			AnalogColumn_InputMUX_1_Bypass_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_Data_ADDR:	0x0
BYTE			AnalogColumn_InputMUX_1_Data_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_DriveMode_0_ADDR:	0x100
BYTE			AnalogColumn_InputMUX_1_DriveMode_0_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_DriveMode_1_ADDR:	0x101
BYTE			AnalogColumn_InputMUX_1_DriveMode_1_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_IntCtrl_0_ADDR:	0x102
BYTE			AnalogColumn_InputMUX_1_IntCtrl_0_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_IntCtrl_1_ADDR:	0x103
BYTE			AnalogColumn_InputMUX_1_IntCtrl_1_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_IntEn_ADDR:	0x1
BYTE			AnalogColumn_InputMUX_1_IntEn_ADDR;
#define AnalogColumn_InputMUX_1_MASK 0x1
// AnalogColumn_InputMUX_2 address and mask defines
#pragma	ioport	AnalogColumn_InputMUX_2_Bypass_ADDR:	0x2
BYTE			AnalogColumn_InputMUX_2_Bypass_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_Data_ADDR:	0x0
BYTE			AnalogColumn_InputMUX_2_Data_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_DriveMode_0_ADDR:	0x100
BYTE			AnalogColumn_InputMUX_2_DriveMode_0_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_DriveMode_1_ADDR:	0x101
BYTE			AnalogColumn_InputMUX_2_DriveMode_1_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_IntCtrl_0_ADDR:	0x102
BYTE			AnalogColumn_InputMUX_2_IntCtrl_0_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_IntCtrl_1_ADDR:	0x103
BYTE			AnalogColumn_InputMUX_2_IntCtrl_1_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_IntEn_ADDR:	0x1
BYTE			AnalogColumn_InputMUX_2_IntEn_ADDR;
#define AnalogColumn_InputMUX_2_MASK 0x2
// AnalogOutBuf_3 address and mask defines
#pragma	ioport	AnalogOutBuf_3_Bypass_ADDR:	0x2
BYTE			AnalogOutBuf_3_Bypass_ADDR;
#pragma	ioport	AnalogOutBuf_3_Data_ADDR:	0x0
BYTE			AnalogOutBuf_3_Data_ADDR;
#pragma	ioport	AnalogOutBuf_3_DriveMode_0_ADDR:	0x100
BYTE			AnalogOutBuf_3_DriveMode_0_ADDR;
#pragma	ioport	AnalogOutBuf_3_DriveMode_1_ADDR:	0x101
BYTE			AnalogOutBuf_3_DriveMode_1_ADDR;
#pragma	ioport	AnalogOutBuf_3_IntCtrl_0_ADDR:	0x102
BYTE			AnalogOutBuf_3_IntCtrl_0_ADDR;
#pragma	ioport	AnalogOutBuf_3_IntCtrl_1_ADDR:	0x103
BYTE			AnalogOutBuf_3_IntCtrl_1_ADDR;
#pragma	ioport	AnalogOutBuf_3_IntEn_ADDR:	0x1
BYTE			AnalogOutBuf_3_IntEn_ADDR;
#define AnalogOutBuf_3_MASK 0x4
// AnalogOutBuf_0 address and mask defines
#pragma	ioport	AnalogOutBuf_0_Bypass_ADDR:	0x2
BYTE			AnalogOutBuf_0_Bypass_ADDR;
#pragma	ioport	AnalogOutBuf_0_Data_ADDR:	0x0
BYTE			AnalogOutBuf_0_Data_ADDR;
#pragma	ioport	AnalogOutBuf_0_DriveMode_0_ADDR:	0x100
BYTE			AnalogOutBuf_0_DriveMode_0_ADDR;
#pragma	ioport	AnalogOutBuf_0_DriveMode_1_ADDR:	0x101
BYTE			AnalogOutBuf_0_DriveMode_1_ADDR;
#pragma	ioport	AnalogOutBuf_0_IntCtrl_0_ADDR:	0x102
BYTE			AnalogOutBuf_0_IntCtrl_0_ADDR;
#pragma	ioport	AnalogOutBuf_0_IntCtrl_1_ADDR:	0x103
BYTE			AnalogOutBuf_0_IntCtrl_1_ADDR;
#pragma	ioport	AnalogOutBuf_0_IntEn_ADDR:	0x1
BYTE			AnalogOutBuf_0_IntEn_ADDR;
#define AnalogOutBuf_0_MASK 0x8
// AnalogOutBuf_2 address and mask defines
#pragma	ioport	AnalogOutBuf_2_Bypass_ADDR:	0x2
BYTE			AnalogOutBuf_2_Bypass_ADDR;
#pragma	ioport	AnalogOutBuf_2_Data_ADDR:	0x0
BYTE			AnalogOutBuf_2_Data_ADDR;
#pragma	ioport	AnalogOutBuf_2_DriveMode_0_ADDR:	0x100
BYTE			AnalogOutBuf_2_DriveMode_0_ADDR;
#pragma	ioport	AnalogOutBuf_2_DriveMode_1_ADDR:	0x101
BYTE			AnalogOutBuf_2_DriveMode_1_ADDR;
#pragma	ioport	AnalogOutBuf_2_IntCtrl_0_ADDR:	0x102
BYTE			AnalogOutBuf_2_IntCtrl_0_ADDR;
#pragma	ioport	AnalogOutBuf_2_IntCtrl_1_ADDR:	0x103
BYTE			AnalogOutBuf_2_IntCtrl_1_ADDR;
#pragma	ioport	AnalogOutBuf_2_IntEn_ADDR:	0x1
BYTE			AnalogOutBuf_2_IntEn_ADDR;
#define AnalogOutBuf_2_MASK 0x10
// AnalogOutBuf_1 address and mask defines
#pragma	ioport	AnalogOutBuf_1_Bypass_ADDR:	0x2
BYTE			AnalogOutBuf_1_Bypass_ADDR;
#pragma	ioport	AnalogOutBuf_1_Data_ADDR:	0x0
BYTE			AnalogOutBuf_1_Data_ADDR;
#pragma	ioport	AnalogOutBuf_1_DriveMode_0_ADDR:	0x100
BYTE			AnalogOutBuf_1_DriveMode_0_ADDR;
#pragma	ioport	AnalogOutBuf_1_DriveMode_1_ADDR:	0x101
BYTE			AnalogOutBuf_1_DriveMode_1_ADDR;
#pragma	ioport	AnalogOutBuf_1_IntCtrl_0_ADDR:	0x102
BYTE			AnalogOutBuf_1_IntCtrl_0_ADDR;
#pragma	ioport	AnalogOutBuf_1_IntCtrl_1_ADDR:	0x103
BYTE			AnalogOutBuf_1_IntCtrl_1_ADDR;
#pragma	ioport	AnalogOutBuf_1_IntEn_ADDR:	0x1
BYTE			AnalogOutBuf_1_IntEn_ADDR;
#define AnalogOutBuf_1_MASK 0x20
// AnalogColumn_InputMUX_2 address and mask defines
#pragma	ioport	AnalogColumn_InputMUX_2_Bypass_ADDR:	0x2
BYTE			AnalogColumn_InputMUX_2_Bypass_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_Data_ADDR:	0x0
BYTE			AnalogColumn_InputMUX_2_Data_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_DriveMode_0_ADDR:	0x100
BYTE			AnalogColumn_InputMUX_2_DriveMode_0_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_DriveMode_1_ADDR:	0x101
BYTE			AnalogColumn_InputMUX_2_DriveMode_1_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_IntCtrl_0_ADDR:	0x102
BYTE			AnalogColumn_InputMUX_2_IntCtrl_0_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_IntCtrl_1_ADDR:	0x103
BYTE			AnalogColumn_InputMUX_2_IntCtrl_1_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_2_IntEn_ADDR:	0x1
BYTE			AnalogColumn_InputMUX_2_IntEn_ADDR;
#define AnalogColumn_InputMUX_2_MASK 0x80