spis.h

用VC编辑的一个MD5算法

/******************************************************************************
*  FILENAME:      SPIS.h
*   VERSION:      Rev B, 2002 Mar 30
*******************************************************************************
*  DESCRIPTION:
*     SPIS SPIS User Module header file.
*******************************************************************************
*	Copyright (c) Cypress MicroSystems 2000-2002. All Rights Reserved.
******************************************************************************/

/* include the global header file */
#include <m8c.h>

/* Create pragmas to support proper argument and return value passing */
#pragma fastcall  SPIS_EnableInt
#pragma fastcall  SPIS_DisableInt
#pragma fastcall  SPIS_Start
#pragma fastcall  SPIS_Stop
#pragma fastcall  SPIS_SetupTxData
#pragma fastcall bSPIS_ReadRxData
#pragma fastcall bSPIS_ReadStatus

/**************************************************
* Prototypes of SPIS API. For a definition of
* functions see SPIS.inc. 
**************************************************/
extern void  SPIS_EnableInt(void);
extern void  SPIS_DisableInt(void);
extern void  SPIS_Start(BYTE bConfiguration);
extern void  SPIS_Stop(void);
extern void  SPIS_SetupTxData(BYTE bTxData);
extern BYTE bSPIS_ReadRxData(void);
extern BYTE bSPIS_ReadStatus(void);	 

/**************************************************
* Defines for SPIS API's. 
**************************************************/

/********************************
* SPI Configuration definitions
********************************/
#define  SPIS_MODE_0                   0x00      // MODE 0 - Leading edge latches data - pos clock
#define  SPIS_MODE_1                   0x02      // MODE 1 - Leading edge latches data - neg clock
#define  SPIS_MODE_2                   0x04      // MODE 2 - Trailing edge latches data - pos clock
#define  SPIS_MODE_3                   0x06      // MODE 3 - Trailing edge latches data - neg clock
#define  SPIS_LSB_FIRST                0x80      // LSB bit transmitted/received first
#define  SPIS_MSB_FIRST                0x00      // MSB bit transmitted/received first

/********************************
* SPI Status register masks
********************************/
#define  SPIS_RX_OVERRUN_ERROR         0x40      // Overrun error in received data
#define  SPIS_TX_BUFFER_EMPTY          0x10      // TX Buffer register is ready for next data byte
#define  SPIS_RX_BUFFER_FULL           0x08      // RX Buffer register has received current data
#define  SPIS_SPI_COMPLETE             0x20      // SPI Tx/Rx cycle has completed

/************************************************
*  Hardware Register Definitions
*************************************************/
#pragma ioport  SPIS_CONTROL_REG:   0x03b                  //Control register
BYTE            SPIS_CONTROL_REG;     
#pragma ioport  SPIS_SHIFT_REG: 0x038                      //TX Shift Register register
BYTE            SPIS_SHIFT_REG;     
#pragma ioport  SPIS_TX_BUFFER_REG: 0x039                  //TX Buffer Register
BYTE            SPIS_TX_BUFFER_REG;     
#pragma ioport  SPIS_RX_BUFFER_REG: 0x03a                  //RX Buffer Register
BYTE            SPIS_RX_BUFFER_REG;     
#pragma ioport  SPIS_FUNCTION_REG:  0x138                  //Function register
BYTE            SPIS_FUNCTION_REG;     
#pragma ioport  SPIS_INPUT_REG: 0x139                      //Input register
BYTE            SPIS_INPUT_REG;     
#pragma ioport  SPIS_OUTPUT_REG:    0x13a                  //Output register
BYTE            SPIS_OUTPUT_REG;     

// end of file