📄 pga_out.lis
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0036 DCA05OU: equ 36h ; Output Register (RW)
0000 ; (Reserved) equ 37h
0000
0000 ; Digital PSoC block 6, Communications Type A
0038 DCA06FN: equ 38h ; Function Register (RW)
0039 DCA06IN: equ 39h ; Input Register (RW)
003A DCA06OU: equ 3Ah ; Output Register (RW)
0000 ; (Reserved) equ 3Bh
0000
0000 ; Digital PSoC block 7, Communications Type A
003C DCA07FN: equ 3Ch ; Function Register (RW)
003D DCA07IN: equ 3Dh ; Input Register (RW)
003E DCA07OU: equ 3Eh ; Output Register (RW)
0000 ; (Reserved) equ 3Fh
0000
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0060 CLK_CR0: equ 60h ; Analog Column Clock Select Register (RW)
00C0 CLK_CR0_AColumn3: equ C0h ; MASK: Specify clock for analog cloumn
0030 CLK_CR0_AColumn2: equ 30h ; MASK: Specify clock for analog cloumn
000C CLK_CR0_AColumn1: equ 0Ch ; MASK: Specify clock for analog cloumn
0003 CLK_CR0_AColumn0: equ 03h ; MASK: Specify clock for analog cloumn
0000
0061 CLK_CR1: equ 61h ; Analog Clock Source Select Register (RW)
0040 CLK_CR1_SHDIS: equ 40h ; MASK: Sample and Hold Disable (all Columns)
0038 CLK_CR1_ACLK1: equ 38h ; MASK: Digital PSoC block for analog source
0007 CLK_CR1_ACLK2: equ 07h ; MASK: Digital PSoC block for analog source
0000
0062 ABF_CR: equ 62h ; Analog Output Buffer Control Register (RW)
00C0 ABF_CR_ACI3: equ C0h ; MASK: Level 1 input mux for analog column 3
0030 ABF_CR_ACI2: equ 30h ; MASK: Level 1 input mux for analog column 2
000C ABF_CR_ACI1: equ 0Ch ; MASK: Level 1 input mux for analog column 1
0003 ABF_CR_ACI0: equ 03h ; MASK: Level 1 input mux for analog column 0
0000
0063 AMD_CR: equ 63h ; Analog Modulator Control Register (RW)
000C AMD_CR_AMOD2: equ 0Ch ; MASK: Modulation source for analog column 2
0003 AMD_CR_AMOD0: equ 03h ; MASK: Modulation source for analog column 1
0000
0000
00E0 OSC_CR0: equ E0h ; System Oscillator Control Register (RW)
0080 OSC_CR0_32K_Select: equ 80h ; MASK: Enable/Disable External XTAL Oscillator
0040 OSC_CR0_PLL_Mode: equ 40h ; MASK: Enable/Disable PLL
0018 OSC_CR0_Sleep: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_Sleep_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_Sleep_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_Sleep_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_Sleep_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System V1/V2 Divider Control Register (RW)
00F0 OSC_CR1_V1: equ F0h ; MASK System V1 24MHz divider
000F OSC_CR1_V2: equ 0Fh ; MASK System V2 24MHz divider
0000
0000 ;Reserved equ E2h
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (WO)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (WO)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (WO)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (WO)
0000
0000
0000
0000 ;;===================================
0000 ;; M8C System Macros
0000 ;;===================================
0000
0000
0000 ;-------------------------------
0000 ; Swapping Register Banks
0000 ;-------------------------------
0000
0000 macro M8C_SetBank0
0000 and F, ~FlagXIOMask
0000 macro M8C_SetBank1
0000 or F, FlagXIOMask
0000 macro M8C_EnableGInt
0000 or F, FlagGlobalIE
0000 macro M8C_DisableGInt
0000 and F, ~FlagGlobalIE
0001 DISABLE_INT_FIX: equ 1
0000 ;---------------------------------------------------
0000 ; Use the following macros to enable/disable
0000 ; either of the two global interrupt mask registers,
0000 ; INT_MSK0 or INT_MSK1.
0000 ;
0000 ; This is a fix to a noted problem in which an
0000 ; inadvertant reset can occur if an interrupt occurs
0000 ; while clearing an interrupt mask bit.
0000 ;
0000 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
0000 ; M8C_EnableIntMask INT_MSKN, MASK
0000 ;
0000 ; where INT_MSKN is INT_MSK0 or INT_MSK1 and
0000 ; MASK is the bit set to enable or disable
0000 ;-------------------------------------------------
0000 ; Disable Interrupt Bit Mask(s)
0000 macro M8C_DisableIntMask
0000 if DISABLE_INT_FIX
0000 mov A, reg[CPU_SCR] ; save the current Global interrupt state
0000 M8C_DisableGInt ; disable global interrupts
0000 endif
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 if DISABLE_INT_FIX
0000 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0000 jz . + 4 ; jump if global interrupt disabled
0000 M8C_EnableGInt ; set global interrupt
0000 endif
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1
0000 macro M8C_EnableWatchDog
0000 ; Clearing the Power-On Reset bit starts up the Watchdog timer
0000 ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
0000 and reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
0003 POWERMASK: equ 03h
00F8 GAINMASK: equ f8h
0000 ;;---------------------------------------------------------------------
0000 ;; StartSetPower: Applies power setting to the module's PSoC block
0000 ;; SetPower: Applies power setting to the module's PSoC block
0000 ;; INPUTS: A contains the power setting 0=Off, 1=Low, 2=Med, 3=High
0000 ;; Value is loaded from .inc file
0000 ;; OUTPUTS: None
0000 ;;---------------------------------------------------------------------
0000 PGA_OUT_Start:
0000 _PGA_OUT_Start:
0000 PGA_OUT_SetPower:
0000 _PGA_OUT_SetPower:
0000
0000 2103 and A, POWERMASK ; mask A to protect unchanged bits
0002 4F mov X, SP ; define temp store location
0003 ;
0003 08 push A ; put power value in temp store
0004 5D7F mov A, reg[PGA_OUT_GAIN_CR2] ; read power value
0006 21FC and A, ~POWERMASK ; clear power bits in A
0008 2B00 or A, [X] ; combine power value with balance of reg.
000A 607F mov reg[PGA_OUT_GAIN_CR2], A ; move complete value back to register
000C 18 pop A
000D 7F ret
000E
000E ;;---------------------------------------------------------------------------------
000E ;; SetGain:
000E ;; INPUTS: Gain value and GAIN/ATTEN setting
000E ;; Use gain set values from .inc file
000E ;; OUTPUTS: None
000E ;;
000E ;; Gain values shown are for example
000E ;; 16.0 1 0 0 0 0
000E ;; 8.00 1 0 0 0 1
000E ;; ....
000E ;; 1.00 1 1 1 1 1
000E ;; 0.93 0 1 1 1 0
000E ;; ....
000E ;; 0.12 0 0 0 0 1
000E ;; 0.06 0 0 0 0 0
000E ;;--------------------------------------------------------------------------------
000E PGA_OUT_SetGain:
000E _PGA_OUT_SetGain:
000E
000E 21F8 and A, GAINMASK ; mask A to protect unchanged bits
0010 4F mov X, SP ; define temp store location
0011 ;
0011 08 push A ; put gain value in temp store
0012 5D7D mov A, reg[PGA_OUT_GAIN_CR0] ; read power value
0014 2107 and A, ~GAINMASK ; clear gain bits in A
0016 2B00 or A, [X] ; combine gain value with balance of reg.
0018 607D mov reg[PGA_OUT_GAIN_CR0], A ; move complete value back to register
001A 18 pop A
001B 7F ret
001C
001C ;;---------------------------------------------------------------------
001C ;; Stop: Cuts power to the user module
001C ;;
001C ;; INPUTS: None
001C ;; OUPTUTS: None
001C ;;---------------------------------------------------------------------
001C PGA_OUT_Stop:
001C _PGA_OUT_Stop:
001C
001C 417FFC and REG[PGA_OUT_GAIN_CR2], ~POWERMASK
001F 7F ret
0020
0020 ;;
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