spis.lis

用VC编辑的一个MD5算法

 0000           ;     none.
 0000           ;
 0000           ;  RETURNS:
 0000           ;     none.
 0000           ;
 0000           ;  SIDE EFFECTS:
 0000           ;     none.
 0000           ;
 0000           ;  THEORY of OPERATION:  
 0000           ;     Sets the specific user module interrupt enable mask bit.
 0000           ;
 0000           ;-----------------------------------------------------------------------------
 0000            SPIS_EnableInt:
 0000           _SPIS_EnableInt:
 0000 43E140        or    reg[SPIS_INT_REG], bSPIS_INT_MASK              
 0003 7F           ret  
 0004           
 0004                   
 0004           ;-----------------------------------------------------------------------------
 0004           ;  FUNCTION NAME: SPIS_DisableInt
 0004           ;
 0004           ;  DESCRIPTION:
 0004           ;     Disables this SPIS's interrupt by clearing the interrupt enable mask bit
 0004           ;     associated with this User Module. 
 0004           ;
 0004           ;  ARGUMENTS:
 0004           ;     none.
 0004           ;
 0004           ;  RETURNS:
 0004           ;     none.
 0004           ;
 0004           ;  SIDE EFFECTS:
 0004           ;     none.
 0004           ;
 0004           ;  THEORY of OPERATION:  
 0004           ;     Clears the specific user module interrupt enable mask bit.
 0004           ;
 0004           ;-----------------------------------------------------------------------------
 0004            SPIS_DisableInt:
 0004           _SPIS_DisableInt:
                if DISABLE_INT_FIX
 0004 5DFF          mov   A, reg[CPU_SCR]           ; save the current Global interrupt state
 0006 70FE          and   F, ~FlagGlobalIE
                endif
 0008 41E1BF        and   reg[SPIS_INT_REG], ~bSPIS_INT_MASK              ; disable specified interrupt enable bit
                if DISABLE_INT_FIX
 000B 2180          and   A, CPUSCR_GIEMask         ; determine if global interrupt was set
 000D A003          jz    . + 4                     ; jump if global interrupt disabled
 000F 7101          or    F, FlagGlobalIE
                endif
 0011 7F           ret
 0012           
 0012           
 0012           ;-----------------------------------------------------------------------------
 0012           ;  FUNCTION NAME: SPIS_Start(BYTE bConfiguration)
 0012           ;
 0012           ;  DESCRIPTION:
 0012           ;     Sets the start bit, SPI mode, and LSB/MSB first configuration of the SPIS 
 0012           ;     user module. 
 0012           ;
 0012           ;     SPIS User Module will be ready to receive data, when an SPI Master initiates
 0012           ;     an SPI transmission/receive protocol cycle.
 0012           ;
 0012           ;  ARGUMENTS:
 0012           ;     BYTE bConfiguration - Consists of SPI Mode and LSB/MSB first bit.  
 0012           ;           Use defined masks - masks can be OR'd together.
 0012           ;     PASSED in Accumulator.
 0012           ;
 0012           ;  RETURNS:
 0012           ;     none.
 0012           ;
 0012           ;  SIDE EFFECTS:
 0012           ;     none.
 0012           ;
 0012           ;  THEORY of OPERATION:  
 0012           ;     Set the specified SPI configuration bits in the Control register.
 0012           ;
 0012           ;-----------------------------------------------------------------------------
 0012            SPIS_Start:
 0012           _SPIS_Start:
 0012              ; setup the SPIS configuration setting 
 0012 2901         or    A, bfCONTROL_REG_START_BIT
 0014 603B         mov   REG[SPIS_CONTROL_REG], A
 0016 7F           ret  
 0017           
 0017           
 0017           ;-----------------------------------------------------------------------------
 0017           ;  FUNCTION NAME: SPIS_Stop
 0017           ;
 0017           ;  DESCRIPTION:
 0017           ;     Disables SPIS operation, and de-asserts the slave select signals.
 0017           ;
 0017           ;  ARGUMENTS:
 0017           ;     none.
 0017           ;
 0017           ;  RETURNS:
 0017           ;     none.
 0017           ;
 0017           ;  SIDE EFFECTS:
 0017           ;     none.
 0017           ;
 0017           ;  THEORY of OPERATION:  
 0017           ;     
 0017           ;     1) Clear the start bit in the Control register.
 0017           ;     2) De-assert slave select signals.
 0017           ;
 0017           ;-----------------------------------------------------------------------------
 0017            SPIS_Stop:
 0017           _SPIS_Stop:
 0017              ; clear the SPIS stop bits
 0017 413BFE       and   REG[SPIS_CONTROL_REG], ~bfCONTROL_REG_START_BIT
 001A 7F           ret  
 001B           
 001B           
 001B           ;-----------------------------------------------------------------------------
 001B           ;  FUNCTION NAME: SPIS_SetupTxData
 001B           ;
 001B           ;  DESCRIPTION:
 001B           ;     Loads data into the SPI Tx Buffer in readiness for an SPI Tx/Rx cycle.  
 001B           ;
 001B           ;  ARGUMENTS:
 001B           ;     BYTE  bTxData - data to transmit.
 001B           ;        Passed in A register
 001B           ;
 001B           ;  RETURNS:
 001B           ;     none.
 001B           ;
 001B           ;  SIDE EFFECTS:
 001B           ;     none.
 001B           ;
 001B           ;  THEORY of OPERATION:  
 001B           ;     1) Writes data into the TX buffer register
 001B           ;
 001B           ;-----------------------------------------------------------------------------
 001B            SPIS_SetupTxData:
 001B           _SPIS_SetupTxData:
 001B 6039              mov REG[SPIS_TX_BUFFER_REG], A
 001D 7F                ret
 001E           
 001E           
 001E           ;-----------------------------------------------------------------------------
 001E           ;  FUNCTION NAME: bSPIS_ReadRxData
 001E           ;
 001E           ;  DESCRIPTION:
 001E           ;     Reads the RX buffer register.  Should check the status regiser to make
 001E           ;     sure data is valid.
 001E           ;
 001E           ;  ARGUMENTS:
 001E           ;     none.
 001E           ;
 001E           ;  RETURNS:
 001E           ;     bRxData - returned in A.
 001E           ;
 001E           ;  SIDE EFFECTS:
 001E           ;     none.
 001E           ;
 001E           ;  THEORY of OPERATION:  
 001E           ;     none.
 001E           ;
 001E           ;-----------------------------------------------------------------------------
 001E            bSPIS_ReadRxData:
 001E           _bSPIS_ReadRxData:
 001E 5D3A              mov A, REG[SPIS_RX_BUFFER_REG]
 0020 7F                ret
 0021           
 0021           
 0021           
 0021           ;-----------------------------------------------------------------------------
 0021           ;  FUNCTION NAME: bSPIS_ReadStatus
 0021           ;
 0021           ;  DESCRIPTION:
 0021           ;     Reads the SPIS Status bits in the Control/Status register.
 0021           ;
 0021           ;  ARGUMENTS:
 0021           ;     none.
 0021           ;
 0021           ;  RETURNS:
 0021           ;     BYTE  bStatus - transmit status data.  Use the defined bit masks.
 0021           ;        Returned in Accumulator.
 0021           ;
 0021           ;  SIDE EFFECTS:
 0021           ;     none.
 0021           ;
 0021           ;  THEORY of OPERATION:  
 0021           ;     Read the status and control register.
 0021           ;
 0021           ;-----------------------------------------------------------------------------
 0021            bSPIS_ReadStatus:
 0021           _bSPIS_ReadStatus:
 0021 5D3B              mov A,  REG[SPIS_CONTROL_REG]
 0023 7F                ret
 0024              
 0024           
 0024           ;       end of SPIS API code
 0024           
 0024           
 0024           
 0024           
 0024