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0062 ABF_CR: equ 62h ; Analog Output Buffer Control Register (RW)
00C0 ABF_CR_ACI3: equ C0h ; MASK: Level 1 input mux for analog column 3
0030 ABF_CR_ACI2: equ 30h ; MASK: Level 1 input mux for analog column 2
000C ABF_CR_ACI1: equ 0Ch ; MASK: Level 1 input mux for analog column 1
0003 ABF_CR_ACI0: equ 03h ; MASK: Level 1 input mux for analog column 0
0000
0063 AMD_CR: equ 63h ; Analog Modulator Control Register (RW)
000C AMD_CR_AMOD2: equ 0Ch ; MASK: Modulation source for analog column 2
0003 AMD_CR_AMOD0: equ 03h ; MASK: Modulation source for analog column 1
0000
0000
00E0 OSC_CR0: equ E0h ; System Oscillator Control Register (RW)
0080 OSC_CR0_32K_Select: equ 80h ; MASK: Enable/Disable External XTAL Oscillator
0040 OSC_CR0_PLL_Mode: equ 40h ; MASK: Enable/Disable PLL
0018 OSC_CR0_Sleep: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_Sleep_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_Sleep_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_Sleep_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_Sleep_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System V1/V2 Divider Control Register (RW)
00F0 OSC_CR1_V1: equ F0h ; MASK System V1 24MHz divider
000F OSC_CR1_V2: equ 0Fh ; MASK System V2 24MHz divider
0000
0000 ;Reserved equ E2h
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (WO)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (WO)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (WO)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (WO)
0000
0000
0000
0000 ;;===================================
0000 ;; M8C System Macros
0000 ;;===================================
0000
0000
0000 ;-------------------------------
0000 ; Swapping Register Banks
0000 ;-------------------------------
0000
0000 macro M8C_SetBank0
0000 and F, ~FlagXIOMask
0000 macro M8C_SetBank1
0000 or F, FlagXIOMask
0000 macro M8C_EnableGInt
0000 or F, FlagGlobalIE
0000 macro M8C_DisableGInt
0000 and F, ~FlagGlobalIE
0001 DISABLE_INT_FIX: equ 1
0000 ;---------------------------------------------------
0000 ; Use the following macros to enable/disable
0000 ; either of the two global interrupt mask registers,
0000 ; INT_MSK0 or INT_MSK1.
0000 ;
0000 ; This is a fix to a noted problem in which an
0000 ; inadvertant reset can occur if an interrupt occurs
0000 ; while clearing an interrupt mask bit.
0000 ;
0000 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
0000 ; M8C_EnableIntMask INT_MSKN, MASK
0000 ;
0000 ; where INT_MSKN is INT_MSK0 or INT_MSK1 and
0000 ; MASK is the bit set to enable or disable
0000 ;-------------------------------------------------
0000 ; Disable Interrupt Bit Mask(s)
0000 macro M8C_DisableIntMask
0000 if DISABLE_INT_FIX
0000 mov A, reg[CPU_SCR] ; save the current Global interrupt state
0000 M8C_DisableGInt ; disable global interrupts
0000 endif
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 if DISABLE_INT_FIX
0000 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0000 jz . + 4 ; jump if global interrupt disabled
0000 M8C_EnableGInt ; set global interrupt
0000 endif
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1
0000 macro M8C_EnableWatchDog
0000 ; Clearing the Power-On Reset bit starts up the Watchdog timer
0000 ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
0000 and reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
0040 bSPIS_INT_MASK: equ 40h
0000 ;SPIS interrupt address
00E1 SPIS_INT_REG: equ 0e1h
0000
0000 ;---------------------------------
0000 ; SPIS PSoC Block Registers
0000 ;---------------------------------
003B SPIS_CONTROL_REG: equ 3bh ;Control register
0038 SPIS_SHIFT_REG: equ 38h ;TX Shift Register register
0039 SPIS_TX_BUFFER_REG: equ 39h ;TX Buffer Register
003A SPIS_RX_BUFFER_REG: equ 3ah ;RX Buffer Register
0038 SPIS_FUNCTION_REG: equ 38h ;Function register
0039 SPIS_INPUT_REG: equ 39h ;Input register
003A SPIS_OUTPUT_REG: equ 3ah ;Output register
0000
0000
0000 ;-------------------------------
0000 ; SPI Configuration definitions
0000 ;-------------------------------
0000 SPIS_MODE_0: equ 00h ;MODE 0 - Leading edge latches data - pos clock
0002 SPIS_MODE_1: equ 02h ;MODE 1 - Leading edge latches data - neg clock
0004 SPIS_MODE_2: equ 04h ;MODE 2 - Trailing edge latches data - pos clock
0006 SPIS_MODE_3: equ 06h ;MODE 3 - Trailing edge latches data - neg clock
0080 SPIS_LSB_FIRST: equ 80h ;LSB bit transmitted/received first
0000 SPIS_MSB_FIRST: equ 00h ;MSB bit transmitted/received first
0000
0000 ;---------------------------
0000 ; SPI Status register masks
0000 ;---------------------------
0040 SPIS_RX_OVERRUN_ERROR: equ 40h ;Overrun error in received data
0010 SPIS_TX_BUFFER_EMPTY: equ 10h ;TX Buffer register is ready for next data byte
0008 SPIS_RX_BUFFER_FULL: equ 08h ;RX Buffer register has received current data
0020 SPIS_SPI_COMPLETE: equ 20h ;SPI Tx/Rx cycle has completed
0000
0000 ; end of file
0000
area text (ROM, REL)
;-------------------------------------------------------------------
; Declare the functions global for both assembler and C compiler.
;
; Note that there are two names for each API. First name is
; assembler reference. Name with underscore is name refence for
; C compiler. Calling function in C source code does not require
; the underscore.
;-------------------------------------------------------------------
export SPIS_EnableInt
export _SPIS_EnableInt
export SPIS_DisableInt
export _SPIS_DisableInt
export SPIS_Start
export _SPIS_Start
export SPIS_Stop
export _SPIS_Stop
export SPIS_SetupTxData
export _SPIS_SetupTxData
export bSPIS_ReadRxData
export _bSPIS_ReadRxData
export bSPIS_ReadStatus
export _bSPIS_ReadStatus
;-----------
; EQUATES
;-----------
0001 bfCONTROL_REG_START_BIT: equ 1 ; Control register start bit
0000
0000 ;-----------------------------------------------------------------------------
0000 ; FUNCTION NAME: SPIS_EnableInt
0000 ;
0000 ; DESCRIPTION:
0000 ; Enables the SPIS interrupt by setting the interrupt enable mask
0000 ; bit associated with this User Module.
0000 ;
0000 ; NOTE: Remember to enable the global interrupt by calling the
0000 ; M8C global macro: M8C_EnableGInt
0000 ;
0000 ; ARGUMENTS:
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