📄 tx_232.lis
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0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
0020 bTx_232_INT_MASK: equ 20h
0000 ;TX8 interrupt address
00E1 Tx_232_INT_REG: equ 0e1h
0000
0000 ;------------------------------------
0000 ; Transmitter Parity masks
0000 ;------------------------------------
0000 TX8_PARITY_NONE: equ 00h
0002 TX8_PARITY_EVEN: equ 02h
0006 TX8_PARITY_ODD: equ 06h
0000
0000 ;------------------------------------
0000 ; Transmitter Status Register masks
0000 ;------------------------------------
0020 TX8_TX_COMPLETE: equ 20h
0010 TX8_TX_BUFFER_EMPTY: equ 10h
0000
0000 ;---------------------------------
0000 ; Registers used by TX8
0000 ;---------------------------------
0037 Tx_232_CONTROL_REG: equ 37h ;Control register
0034 Tx_232_TX_SHIFT_REG: equ 34h ;TX Shift Register register
0035 Tx_232_TX_BUFFER_REG: equ 35h ;TX Buffer Register
0034 Tx_232_FUNC_REG: equ 34h ;Function register
0035 Tx_232_INPUT_REG: equ 35h ;Input register
0036 Tx_232_OUTPUT_REG: equ 36h ;Output register
0000
0000 ; end of file
0000
area text (ROM, REL)
;-------------------------------------------------------------------
; Declare the functions global for both assembler and C compiler.
;
; Note that there are two names for each API. First name is
; assembler reference. Name with underscore is name refence for
; C compiler. Calling function in C source code does not require
; the underscore.
;-------------------------------------------------------------------
export Tx_232_EnableInt
export _Tx_232_EnableInt
export Tx_232_DisableInt
export _Tx_232_DisableInt
export Tx_232_Start
export _Tx_232_Start
export Tx_232_Stop
export _Tx_232_Stop
export Tx_232_SendData
export _Tx_232_SendData
export bTx_232_ReadTxStatus
export _bTx_232_ReadTxStatus
;-----------
; EQUATES
;-----------
0001 bfCONTROL_REG_START_BIT: equ 1 ; Control register start bit
0000
0000 ;-----------------------------------------------------------------------------
0000 ; FUNCTION NAME: Tx_232_EnableInt
0000 ;
0000 ; DESCRIPTION:
0000 ; Enables this Transmitter's interrupt by setting the interrupt enable mask
0000 ; bit associated with this User Module. Remember to call the global interrupt
0000 ; enable function by using the macro: M8C_EnableGInt.
0000 ;
0000 ; ARGUMENTS:
0000 ; none.
0000 ;
0000 ; RETURNS:
0000 ; none.
0000 ;
0000 ; SIDE EFFECTS:
0000 ; none.
0000 ;
0000 ; THEORY of OPERATION:
0000 ; Sets the specific user module interrupt enable mask bit.
0000 ;
0000 ;-----------------------------------------------------------------------------
0000 Tx_232_EnableInt:
0000 _Tx_232_EnableInt:
0000 43E120 or reg[Tx_232_INT_REG], bTx_232_INT_MASK
0003 7F ret
0004
0004
0004 ;-----------------------------------------------------------------------------
0004 ; FUNCTION NAME: Tx_232_DisableInt
0004 ;
0004 ; DESCRIPTION:
0004 ; Disables this TX8's interrupt by clearing the interrupt enable mask bit
0004 ; associated with this User Module.
0004 ;
0004 ; ARGUMENTS:
0004 ; none.
0004 ;
0004 ; RETURNS:
0004 ; none.
0004 ;
0004 ; SIDE EFFECTS:
0004 ; none.
0004 ;
0004 ; THEORY of OPERATION:
0004 ; Clears the specific user module interrupt enable mask bit.
0004 ;
0004 ;-----------------------------------------------------------------------------
0004 Tx_232_DisableInt:
0004 _Tx_232_DisableInt:
if DISABLE_INT_FIX
0004 5DFF mov A, reg[CPU_SCR] ; save the current Global interrupt state
0006 70FE and F, ~FlagGlobalIE
endif
0008 41E1DF and reg[Tx_232_INT_REG], ~bTx_232_INT_MASK ; disable specified interrupt enable bit
if DISABLE_INT_FIX
000B 2180 and A, CPUSCR_GIEMask ; determine if global interrupt was set
000D A003 jz . + 4 ; jump if global interrupt disabled
000F 7101 or F, FlagGlobalIE
endif
0011 7F ret
0012
0012
0012 ;-----------------------------------------------------------------------------
0012 ; FUNCTION NAME: Tx_232_Start(BYTE bParity)
0012 ;
0012 ; DESCRIPTION:
0012 ; Sets the start bit and parity in the Control register of this user module.
0012 ; The transmitter will begin transmitting if a byte has been written into the
0012 ; transmit buffer.
0012 ;
0012 ; ARGUMENTS:
0012 ; BYTE bParity - parity of transmitted data. Use defined masks.
0012 ;
0012 ; RETURNS:
0012 ; none.
0012 ;
0012 ; SIDE EFFECTS:
0012 ; none.
0012 ;
0012 ; THEORY of OPERATION:
0012 ; Set the specified parity and start bits in the Control register.
0012 ;
0012 ;-----------------------------------------------------------------------------
0012 Tx_232_Start:
0012 _Tx_232_Start:
0012 2901 or A, bfCONTROL_REG_START_BIT
0014 6037 mov REG[Tx_232_CONTROL_REG], A
0016 7F ret
0017
0017
0017 ;-----------------------------------------------------------------------------
0017 ; FUNCTION NAME: Tx_232_Stop
0017 ;
0017 ; DESCRIPTION:
0017 ; Disables TX8 operation.
0017 ;
0017 ; ARGUMENTS:
0017 ; none.
0017 ;
0017 ; RETURNS:
0017 ; none.
0017 ;
0017 ; SIDE EFFECTS:
0017 ; none.
0017 ;
0017 ; THEORY of OPERATION:
0017 ; Clear the start bit in the Control register.
0017 ;
0017 ;-----------------------------------------------------------------------------
0017 Tx_232_Stop:
0017 _Tx_232_Stop:
0017 4137FE and REG[Tx_232_CONTROL_REG], ~bfCONTROL_REG_START_BIT
001A 7F ret
001B
001B
001B ;-----------------------------------------------------------------------------
001B ; FUNCTION NAME: Tx_232_SendData
001B ;
001B ; DESCRIPTION:
001B ; Disables TX8 operation.
001B ;
001B ; ARGUMENTS:
001B ; BYTE TxData - data to transmit.
001B ;
001B ; RETURNS:
001B ; none.
001B ;
001B ; SIDE EFFECTS:
001B ; none.
001B ;
001B ; THEORY of OPERATION:
001B ; Writes data to the TX buffer register.
001B ;
001B ;-----------------------------------------------------------------------------
001B Tx_232_SendData:
001B _Tx_232_SendData:
001B 6035 mov REG[Tx_232_TX_BUFFER_REG], A
001D 7F ret
001E
001E
001E ;-----------------------------------------------------------------------------
001E ; FUNCTION NAME: bTx_232_ReadTxStatus
001E ;
001E ; DESCRIPTION:
001E ; Reads the Tx Status bits in the Control/Status register.
001E ;
001E ; ARGUMENTS:
001E ; none.
001E ;
001E ; RETURNS:
001E ; BYTE bTxStatus - transmit status data. Use the following defined bits
001E ; masks: TX_COMPLETE and TX_BUFFER_EMPTY
001E ;
001E ; SIDE EFFECTS:
001E ; none.
001E ;
001E ; THEORY of OPERATION:
001E ; Read the status and control register.
001E ;
001E ;-----------------------------------------------------------------------------
001E bTx_232_ReadTxStatus:
001E _bTx_232_ReadTxStatus:
001E 5D37 mov A, REG[Tx_232_CONTROL_REG]
0020 7F ret
0021
0021
0021 ; end of TX8 API code
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