spisint.lis

用VC编辑的一个MD5算法

 0000           ;------------------------------------------------------------------------------
 0000           ;  FILENAME:   SPISint.asm
 0000           ;   VERSION:   Rev B, 2002 Mar 30
 0000           ;------------------------------------------------------------------------------
 0000           ;  DESCRIPTION:
 0000           ;     Interrupt handler routine for SPIS user module instance:
 0000           ;        SPIS.
 0000           ;------------------------------------------------------------------------------
 0000           ;       Copyright (c) Cypress MicroSystems 2000-2002.  All Rights Reserved.
 0000           ;------------------------------------------------------------------------------
 0000           
 0040           bSPIS_INT_MASK:             equ 40h  
 0000           ;SPIS interrupt address
 00E1           SPIS_INT_REG:               equ 0e1h  
 0000           
 0000           ;---------------------------------
 0000           ; SPIS PSoC Block Registers
 0000           ;---------------------------------
 003B           SPIS_CONTROL_REG:   equ 3bh                      ;Control register
 0038           SPIS_SHIFT_REG: equ 38h                          ;TX Shift Register register
 0039           SPIS_TX_BUFFER_REG: equ 39h                      ;TX Buffer Register
 003A           SPIS_RX_BUFFER_REG: equ 3ah                      ;RX Buffer Register
 0038           SPIS_FUNCTION_REG:  equ 38h                      ;Function register
 0039           SPIS_INPUT_REG: equ 39h                          ;Input register
 003A           SPIS_OUTPUT_REG:    equ 3ah                      ;Output register
 0000           
 0000           
 0000           ;-------------------------------
 0000           ; SPI Configuration definitions
 0000           ;-------------------------------
 0000           SPIS_MODE_0:                  equ   00h      ;MODE 0 - Leading edge latches data - pos clock
 0002           SPIS_MODE_1:                  equ   02h      ;MODE 1 - Leading edge latches data - neg clock
 0004           SPIS_MODE_2:                  equ   04h      ;MODE 2 - Trailing edge latches data - pos clock
 0006           SPIS_MODE_3:                  equ   06h      ;MODE 3 - Trailing edge latches data - neg clock
 0080           SPIS_LSB_FIRST:               equ   80h      ;LSB bit transmitted/received first
 0000           SPIS_MSB_FIRST:               equ   00h      ;MSB bit transmitted/received first
 0000           
 0000           ;---------------------------
 0000           ; SPI Status register masks
 0000           ;---------------------------
 0040           SPIS_RX_OVERRUN_ERROR:        equ   40h      ;Overrun error in received data
 0010           SPIS_TX_BUFFER_EMPTY:         equ   10h      ;TX Buffer register is ready for next data byte
 0008           SPIS_RX_BUFFER_FULL:          equ   08h      ;RX Buffer register has received current data
 0020           SPIS_SPI_COMPLETE:            equ   20h      ;SPI Tx/Rx cycle has completed
 0000           
 0000           ; end of file
 0000           
                area text (ROM, REL)
                
                ;-----------------------------------------------------
                ;  Export interrupt handler
                ;     NOTE that interrupt handler is NOT exported
                ;     for access by C function.  Interrupt handlers
                ;     are not callable by C functions.
                ;-----------------------------------------------------
                export   SPISINT
                
                ;-----------------------------------------------------------------------------
                ;  FUNCTION NAME: SPISInt
                ;
                ;  DESCRIPTION:
                ;     SPIS interrupt handler for instance SPIS.  
                ;
                ;     This is a place holder function.  If the user requires use of an interrupt
                ;     handler for this function, then place code where specified.
                ;
                ;  ARGUMENTS:
                ;     none.
                ;
                ;  RETURNS:
                ;     none.
                ;
                ;  SIDE EFFECTS:
                ;     none.
                ;
                ;  THEORY of OPERATION:  
                ;     1) De-assert all slave select signals.
                ;     2) Exercise further SPIS interrupt level processing.
                ;
                ;-----------------------------------------------------------------------------
 0000           SPISINT:
 0000              ;---------------------------------------------------------
 0000              ; Place additional SPIS interrupt level processing here!!!
 0000              ;---------------------------------------------------------
 0000           
 0000 7E           reti
 0001                   
 0001           
 0001           ; end of file
 0001