📄 dac.lis
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0000 ;;************************************************************************
0000 ;;
0000 ;; DAC.asm (from dac9.asm user module template)
0000 ;; Rev A, 2002 Jul 18
0000 ;;
0000 ;; Assembler source for 9-bit Switched Capacitor DAC API
0000 ;;
0000 ;; Copyright (c) Cypress MicroSystems 2002. All Rights Reserved.
0000 ;;
0000 ;;************************************************************************
0000
export DAC_Start
export _DAC_Start
export DAC_SetPower
export _DAC_SetPower
export DAC_WriteBlind
export _DAC_WriteBlind
export DAC_WriteBlind2B
export _DAC_WriteBlind2B
export DAC_WriteStall
export _DAC_WriteStall
export DAC_WriteStall2B
export _DAC_WriteStall2B
export DAC_Stop
export _DAC_Stop
;; -----------------------------------------------------------------
;; Register Definitions
;; -----------------------------------------------------------------
;;
;; Uses 2 Switched Cap Blocks, LSB and MSB, configured as shown below.
;; This API depends on knowing the exact personalization of CR0
;; and CR3 bitfields for time efficiency.
;;
;; * For a Mask/Val pair this simply indicates that the value is
;; determined by the user either through config-time parameteriza-
;; tion or run-time manipulation.
;;
;; Setting for output=AGND to OBUS when LSB in ASA10 and MSB in ASB20:
;; LSB.CR0=80 MSB.CR0=80
;; LSB.CR1=40 MSB.CR1=81
;; LSB.CR2=20 MSB.CR2=A0
;; LSB.CR3=33 MSB.CR3=3B
;;
;; BIT FIELD Mask/Val Function
;; ----------------- -------- --------------------
;; LSB.CR0.FCap 80/1 Feedback cap size 32
;; LSB.CR0.ClockPhase 40/0 Normal phase
;; LSB.CR0.ASign 20/* User parameter
;; LSB.CR0.ACap 1F/* User parameter
;;
;; LSB.CR1.ACMux E0/2 (SCA) A:VRef High, C:Don't Care
;; LSB.CR1.BCap 1F/0 Prune B-input branch
;;
;; LSB.CR2.AnalogBus 80/* User Parameter: Output Bus Enable
;; LSB.CR2.CmpBus 40/0 Comparator Bus Disabled
;; LSB.CR2.AutoZero 20/1 Auto-Zero enabled on internal Phi 1
;; LSB.CR2.CCap 1F/0 Prune C-input branch
;;
;; LSB.CR3.ARefSelect C0/0 Use AGND (to invert)
;; LSB.CR3.FSW1 20/1 Feedback Cap Used
;; LSB.CR3.FSW0 10/1 Feedback Cap Grounded for AZ
;; LSB.CR3.BMux 0C/0 (SCA) Don't Care - this branch pruned
;; LSB.CR3.PWR 03/* User Parameter: Power; default=OFF
;;
;; MSB.CR0.FCap 80/1 Feedback cap size 32
;; MSB.CR0.ClockPhase 40/0 Normal phase
;; MSB.CR0.ASign 20/* User parameter
;; MSB.CR0.ACap 1F/* User parameter
;;
;; MSB.CR1.AMux E0/4 (SCB) VRef High
;; MSB.CR1.BCap 1F/1 Subrange LSB block output by BCap/FCap (1/32)
;;
;; MSB.CR2.AnalogBus 80/* User Parameter: Output Bus Enable
;; MSB.CR2.CmpBus 40/0 Comparator Bus Disable
;; MSB.CR2.AutoZero 20/1 Auto-Zero enabled on internal Phi 1
;; MSB.CR2.CCap 1F/0 Prune C-input branch
;;
;; MSB.CR3.ARefSelect C0/0 Use AGND (to invert)
;; MSB.CR3.FSW1 20/1 Feedback Cap Used
;; MSB.CR3.FSW2 10/1 Feedback Cap Grounded for AZ
;; MSB.CR3.BSW 08/0 (SCB) why is this cont time instead of phi2??
;; MSB.CR3.BMux 04/? (SCB) LSB block output; determined by placement
;; MSB.CR3.PWR 03/* User Parameter: Power, default=OFF
0000 DAC_OFF: equ 00h
0001 DAC_LOWPOWER: equ 01h
0002 DAC_MEDPOWER: equ 02h
0003 DAC_FULLPOWER: equ 03h
0000
0090 DAC_LSB_CR0: equ 90h
0091 DAC_LSB_CR1: equ 91h
0092 DAC_LSB_CR2: equ 92h
0093 DAC_LSB_CR3: equ 93h
0080 DAC_MSB_CR0: equ 80h
0081 DAC_MSB_CR1: equ 81h
0082 DAC_MSB_CR2: equ 82h
0083 DAC_MSB_CR3: equ 83h
0000
0004 DAC_OffsetBinary: equ 04h
0002 DAC_TwosComplement: equ 02h
0001 DAC_SignAndMagnitude: equ 01h
0000 DAC_RawRegister: equ 00h
0000
0001 DAC_DATAFORMAT: equ 1h
0000 DAC_OFFSETBINARY: equ DAC_DATAFORMAT & DAC_OffsetBinary
0000 DAC_TWOSCOMPLEMENT: equ DAC_DATAFORMAT & DAC_TwosComplement
0001 DAC_SIGNANDMAGNITUDE: equ DAC_DATAFORMAT & DAC_SignAndMagnitude
0000
0000 DAC_PHASE_Normal: equ 0
0001 DAC_PHASE_Swapped: equ 1
0000
0000 DAC_PHASE_SWAP: equ DAC_PHASE_Normal
0000
IF DAC_PHASE_SWAP
DAC_CR0_HIBITS: equ C0h
ELSE
0080 DAC_CR0_HIBITS: equ 80h
ENDIF
0010 FlagXIOMask: equ 10h
0008 FlagSuper: equ 08h
0004 FlagCarry: equ 04h
0002 FlagZero: equ 02h
0001 FlagGlobalIE: equ 01h
0000
0000
0000 ;;===================================
0000 ;; Register Space, Bank 0
0000 ;;===================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (WO)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (WO)
0000 ; (Reserved) equ 03h
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (WO)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (WO)
0000 ; (Reserved) equ 07h
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (WO)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (WO)
0000 ; (Reserved) equ 0Bh
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (WO)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (WO)
0000 ; (Reserved) equ 0Fh
0000 ; Port 4
0010 PRT4DR: equ 10h ; Port 4 Data Register (RW)
0011 PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (WO)
0012 PRT4GS: equ 12h ; Port 4 Global Select Register (WO)
0000 ; (Reserved) equ 13h
0000 ; Port 5
0014 PRT5DR: equ 14h ; Port 5 Data Register (RW)
0015 PRT5IE: equ 15h ; Port 5 Interrupt Enable Register (WO)
0016 PRT5GS: equ 16h ; Port 5 Global Select Register (WO)
0000 ; (Reserved) equ 17h
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 0, Basic Type A
0020 DBA00DR0: equ 20h ; data register 0 (RO)
0021 DBA00DR1: equ 21h ; data register 1 (WO)
0022 DBA00DR2: equ 22h ; data register 2 (RW)
0023 DBA00CR0: equ 23h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 1, Basic Type A
0024 DBA01DR0: equ 24h ; data register 0 (RO)
0025 DBA01DR1: equ 25h ; data register 1 (WO)
0026 DBA01DR2: equ 26h ; data register 2 (RW)
0027 DBA01CR0: equ 27h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 2, Basic Type A
0028 DBA02DR0: equ 28h ; data register 0 (RO)
0029 DBA02DR1: equ 29h ; data register 1 (WO)
002A DBA02DR2: equ 2Ah ; data register 2 (RW)
002B DBA02CR0: equ 2Bh ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 3, Basic Type A
002C DBA03DR0: equ 2Ch ; data register 0 (RO)
002D DBA03DR1: equ 2Dh ; data register 1 (WO)
002E DBA03DR2: equ 2Eh ; data register 2 (RW)
002F DBA03CR0: equ 2Fh ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 4, Communications Type A
0030 DCA04DR0: equ 30h ; data register 0 (RO)
0031 DCA04DR1: equ 31h ; data register 1 (WO)
0032 DCA04DR2: equ 32h ; data register 2 (RW)
0033 DCA04CR0: equ 33h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 5, Communications Type A
0034 DCA05DR0: equ 34h ; data register 0 (RO)
0035 DCA05DR1: equ 35h ; data register 1 (WO)
0036 DCA05DR2: equ 36h ; data register 2 (RW)
0037 DCA05CR0: equ 37h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 6, Communications Type A
0038 DCA06DR0: equ 38h ; data register 0 (RO)
0039 DCA06DR1: equ 39h ; data register 1 (WO)
003A DCA06DR2: equ 3Ah ; data register 2 (RW)
003B DCA06CR0: equ 3Bh ; control & status register 0 (RW)
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