📄 psocconfigtbl.lis
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0000
0000
0000 ;;===================================
0000 ;; M8C System Macros
0000 ;;===================================
0000
0000
0000 ;-------------------------------
0000 ; Swapping Register Banks
0000 ;-------------------------------
0000
0000 macro M8C_SetBank0
0000 and F, ~FlagXIOMask
0000 macro M8C_SetBank1
0000 or F, FlagXIOMask
0000 macro M8C_EnableGInt
0000 or F, FlagGlobalIE
0000 macro M8C_DisableGInt
0000 and F, ~FlagGlobalIE
0001 DISABLE_INT_FIX: equ 1
0000 ;---------------------------------------------------
0000 ; Use the following macros to enable/disable
0000 ; either of the two global interrupt mask registers,
0000 ; INT_MSK0 or INT_MSK1.
0000 ;
0000 ; This is a fix to a noted problem in which an
0000 ; inadvertant reset can occur if an interrupt occurs
0000 ; while clearing an interrupt mask bit.
0000 ;
0000 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
0000 ; M8C_EnableIntMask INT_MSKN, MASK
0000 ;
0000 ; where INT_MSKN is INT_MSK0 or INT_MSK1 and
0000 ; MASK is the bit set to enable or disable
0000 ;-------------------------------------------------
0000 ; Disable Interrupt Bit Mask(s)
0000 macro M8C_DisableIntMask
0000 if DISABLE_INT_FIX
0000 mov A, reg[CPU_SCR] ; save the current Global interrupt state
0000 M8C_DisableGInt ; disable global interrupts
0000 endif
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 if DISABLE_INT_FIX
0000 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0000 jz . + 4 ; jump if global interrupt disabled
0000 M8C_EnableGInt ; set global interrupt
0000 endif
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1
0000 macro M8C_EnableWatchDog
0000 ; Clearing the Power-On Reset bit starts up the Watchdog timer
0000 ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
0000 and reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
export LoadConfigTBL_dds
AREA psoc_config(rom, rel)
0000 LoadConfigTBL_dds:
0000 7110 or F, FlagXIOMask
0002 ; Global Register values
0002 626100 mov reg[61h], 00h ; AnalogClockSelect register (CLK_CR1)
0005 626001 mov reg[60h], 01h ; AnalogColumnClockSelect register (CLK_CR0)
0008 6262FD mov reg[62h], fdh ; AnalogIOControl register (ABF_CR)
000B 626300 mov reg[63h], 00h ; AnalogModulatorControl register (AMD_CR)
000E 62E15F mov reg[e1h], 5fh ; OscillatorControl_1 register (OSC_CR1)
0011 620000 mov reg[00h], 00h ; Port_0_DriveMode_0 register (PRT0DM0)
0014 6201BF mov reg[01h], bfh ; Port_0_DriveMode_1 register (PRT0DM1)
0017 620200 mov reg[02h], 00h ; Port_0_IntCtrl_0 register (PRT0IC0)
001A 620300 mov reg[03h], 00h ; Port_0_IntCtrl_1 register (PRT0IC1)
001D 620460 mov reg[04h], 60h ; Port_1_DriveMode_0 register (PRT1DM0)
0020 620590 mov reg[05h], 90h ; Port_1_DriveMode_1 register (PRT1DM1)
0023 620600 mov reg[06h], 00h ; Port_1_IntCtrl_0 register (PRT1IC0)
0026 620700 mov reg[07h], 00h ; Port_1_IntCtrl_1 register (PRT1IC1)
0029 620800 mov reg[08h], 00h ; Port_2_DriveMode_0 register (PRT2DM0)
002C 620900 mov reg[09h], 00h ; Port_2_DriveMode_1 register (PRT2DM1)
002F 620A00 mov reg[0ah], 00h ; Port_2_IntCtrl_0 register (PRT2IC0)
0032 620B00 mov reg[0bh], 00h ; Port_2_IntCtrl_1 register (PRT2IC1)
0035 620C00 mov reg[0ch], 00h ; Port_3_DriveMode_0 register (PRT3DM0)
0038 620D00 mov reg[0dh], 00h ; Port_3_DriveMode_1 register (PRT3DM1)
003B 620E00 mov reg[0eh], 00h ; Port_3_IntCtrl_0 register (PRT3IC0)
003E 620F00 mov reg[0fh], 00h ; Port_3_IntCtrl_1 register (PRT3IC1)
0041 621000 mov reg[10h], 00h ; Port_4_DriveMode_0 register (PRT4DM0)
0044 621100 mov reg[11h], 00h ; Port_4_DriveMode_1 register (PRT4DM1)
0047 621200 mov reg[12h], 00h ; Port_4_IntCtrl_0 register (PRT4IC0)
004A 621300 mov reg[13h], 00h ; Port_4_IntCtrl_1 register (PRT4IC1)
004D 621400 mov reg[14h], 00h ; Port_5_DriveMode_0 register (PRT5DM0)
0050 621500 mov reg[15h], 00h ; Port_5_DriveMode_1 register (PRT5DM1)
0053 621600 mov reg[16h], 00h ; Port_5_IntCtrl_0 register (PRT5IC0)
0056 621700 mov reg[17h], 00h ; Port_5_IntCtrl_1 register (PRT5IC1)
0059 62E387 mov reg[e3h], 87h ; VoltageMonitorControl register (VLT_CR)
005C ; Instance name DAC, User Module DAC9
005C ; Instance name DAC, Block Name LSB(ASB20)
005C ; Instance name DAC, Block Name MSB(ASA10)
005C ; Instance name PGA_FIL1, User Module PGA_A
005C ; Instance name PGA_FIL1, Block Name GAIN(ACA01)
005C ; Instance name PGA_FIL2, User Module PGA_A
005C ; Instance name PGA_FIL2, Block Name GAIN(ACA02)
005C ; Instance name PGA_OUT, User Module PGA_A
005C ; Instance name PGA_OUT, Block Name GAIN(ACA03)
005C ; Instance name Rs_Timer, User Module Timer8
005C ; Instance name Rs_Timer, Block Name TIMER8(DBA03)
005C 622C20 mov reg[2ch], 20h ;Rs_Timer_FUNC_REG (DBA03FN)
005F 622D05 mov reg[2dh], 05h ;Rs_Timer_INPUT_REG (DBA03IN)
0062 622E00 mov reg[2eh], 00h ;Rs_Timer_OUTPUT_REG (DBA03OU)
0065 ; Instance name Rx_232, User Module RX8
0065 ; Instance name Rx_232, Block Name RX8(DCA04)
0065 623005 mov reg[30h], 05h ;Rx_232_FUNC_REG (DCA04FN)
0068 6231F2 mov reg[31h], f2h ;Rx_232_INPUT_REG (DCA04IN)
006B 623200 mov reg[32h], 00h ;Rx_232_OUTPUT_REG (DCA04OU)
006E ; Instance name SPIS, User Module SPIS
006E ; Instance name SPIS, Block Name SPIS(DCA06)
006E 62381E mov reg[38h], 1eh ;SPIS_FUNCTION_REG (DCA06FN)
0071 623964 mov reg[39h], 64h ;SPIS_INPUT_REG (DCA06IN)
0074 623A06 mov reg[3ah], 06h ;SPIS_OUTPUT_REG (DCA06OU)
0077 ; Instance name Tx_232, User Module TX8
0077 ; Instance name Tx_232, Block Name TX8(DCA05)
0077 62340D mov reg[34h], 0dh ;Tx_232_FUNC_REG (DCA05FN)
007A 623502 mov reg[35h], 02h ;Tx_232_INPUT_REG (DCA05IN)
007D 623605 mov reg[36h], 05h ;Tx_232_OUTPUT_REG (DCA05OU)
0080 70EF and F, ~FlagXIOMask
0082 ; Global Register values
0082 626030 mov reg[60h], 30h ; AnalogColumnInputSelect register (AMX_IN)
0085 626400 mov reg[64h], 00h ; AnalogComparatorControl register (CMP_CR)
0088 626345 mov reg[63h], 45h ; AnalogReferenceControl register (ARF_CR)
008B 626500 mov reg[65h], 00h ; AnalogSyncControl register (ASY_CR)
008E 62E600 mov reg[e6h], 00h ; DecimatorControl register (DEC_CR)
0091 620200 mov reg[02h], 00h ; Port_0_Bypass register (PRT0GS)
0094 620100 mov reg[01h], 00h ; Port_0_IntEn register (PRT0IE)
0097 6206F0 mov reg[06h], f0h ; Port_1_Bypass register (PRT1GS)
009A 620500 mov reg[05h], 00h ; Port_1_IntEn register (PRT1IE)
009D 620A00 mov reg[0ah], 00h ; Port_2_Bypass register (PRT2GS)
00A0 620900 mov reg[09h], 00h ; Port_2_IntEn register (PRT2IE)
00A3 620E00 mov reg[0eh], 00h ; Port_3_Bypass register (PRT3GS)
00A6 620D00 mov reg[0dh], 00h ; Port_3_IntEn register (PRT3IE)
00A9 621200 mov reg[12h], 00h ; Port_4_Bypass register (PRT4GS)
00AC 621100 mov reg[11h], 00h ; Port_4_IntEn register (PRT4IE)
00AF 621600 mov reg[16h], 00h ; Port_5_Bypass register (PRT5GS)
00B2 621500 mov reg[15h], 00h ; Port_5_IntEn register (PRT5IE)
00B5 ; Instance name DAC, User Module DAC9
00B5 ; Instance name DAC, Block Name LSB(ASB20)
00B5 629080 mov reg[90h], 80h ;DAC_LSB_CR0(ASB20CR0)
00B8 629180 mov reg[91h], 80h ;DAC_LSB_CR1(ASB20CR1)
00BB 629220 mov reg[92h], 20h ;DAC_LSB_CR2(ASB20CR2)
00BE 629330 mov reg[93h], 30h ;DAC_LSB_CR3(ASB20CR3)
00C1 ; Instance name DAC, Block Name MSB(ASA10)
00C1 6280A0 mov reg[80h], a0h ;DAC_MSB_CR0(ASA10CR0)
00C4 628141 mov reg[81h], 41h ;DAC_MSB_CR1(ASA10CR1)
00C7 6282A0 mov reg[82h], a0h ;DAC_MSB_CR2(ASA10CR2)
00CA 62833C mov reg[83h], 3ch ;DAC_MSB_CR3(ASA10CR3)
00CD ; Instance name PGA_FIL1, User Module PGA_A
00CD ; Instance name PGA_FIL1, Block Name GAIN(ACA01)
00CD 6275FD mov reg[75h], fdh ;PGA_FIL1_GAIN_CR0(ACA01CR0)
00D0 6276A1 mov reg[76h], a1h ;PGA_FIL1_GAIN_CR1(ACA01CR1)
00D3 627720 mov reg[77h], 20h ;PGA_FIL1_GAIN_CR2(ACA01CR2)
00D6 ; Instance name PGA_FIL2, User Module PGA_A
00D6 ; Instance name PGA_FIL2, Block Name GAIN(ACA02)
00D6 6279FD mov reg[79h], fdh ;PGA_FIL2_GAIN_CR0(ACA02CR0)
00D9 627AA1 mov reg[7ah], a1h ;PGA_FIL2_GAIN_CR1(ACA02CR1)
00DC 627B20 mov reg[7bh], 20h ;PGA_FIL2_GAIN_CR2(ACA02CR2)
00DF ; Instance name PGA_OUT, User Module PGA_A
00DF ; Instance name PGA_OUT, Block Name GAIN(ACA03)
00DF 627DFD mov reg[7dh], fdh ;PGA_OUT_GAIN_CR0(ACA03CR0)
00E2 627EA2 mov reg[7eh], a2h ;PGA_OUT_GAIN_CR1(ACA03CR1)
00E5 627F20 mov reg[7fh], 20h ;PGA_OUT_GAIN_CR2(ACA03CR2)
00E8 ; Instance name Rs_Timer, User Module Timer8
00E8 ; Instance name Rs_Timer, Block Name TIMER8(DBA03)
00E8 622F00 mov reg[2fh], 00h ;Rs_Timer_CONTROL_REG(DBA03CR0)
00EB 622D00 mov reg[2dh], 00h ;Rs_Timer_PERIOD_REG (DBA03DR1)
00EE 622E00 mov reg[2eh], 00h ;Rs_Timer_COMPARE_REG(DBA03DR2)
00F1 ; Instance name Rx_232, User Module RX8
00F1 ; Instance name Rx_232, Block Name RX8(DCA04)
00F1 623100 mov reg[31h], 00h ;Rx_232_(DCA04DR1)
00F4 623200 mov reg[32h], 00h ;Rx_232_RX_BUFFER_REG(DCA04DR2)
00F7 ; Instance name SPIS, User Module SPIS
00F7 ; Instance name SPIS, Block Name SPIS(DCA06)
00F7 623900 mov reg[39h], 00h ;SPIS_TX_BUFFER_REG(DCA06DR1)
00FA 623A00 mov reg[3ah], 00h ;SPIS_RX_BUFFER_REG(DCA06DR2)
00FD ; Instance name Tx_232, User Module TX8
00FD ; Instance name Tx_232, Block Name TX8(DCA05)
00FD 623500 mov reg[35h], 00h ;Tx_232_TX_BUFFER_REG(DCA05DR1)
0100 623600 mov reg[36h], 00h ;Tx_232_(DCA05DR2)
0103 7F ret
0104
0104
0104 ; PSoC Configuration file trailer PsocConfig.asm
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