📄 psocconfigtbl.lis
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009D ASA23CR1: equ 9Dh ; Control register 1 (RW)
009E ASA23CR2: equ 9Eh ; Control register 2 (RW)
009F ASA23CR3: equ 9Fh ; Control register 3 (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
00E0 INT_MSK0: equ E0h ; General Interrupt Mask Register (RW)
0040 INT_MSK0_Sleep: equ 40h ; MASK: enable/disable sleep interrupt
0020 INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
0010 INT_MSK0_AColumn3: equ 10h ; MASK: enable/disable Analog col 3 interrupt
0008 INT_MSK0_AColumn2: equ 08h ; MASK: enable/disable Analog col 2 interrupt
0004 INT_MSK0_AColumn1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
0002 INT_MSK0_AColumn0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
0001 INT_MSK0_VoltageMonitor: equ 01h ; MASK: enable/disable Volts interrupt
0000
00E1 INT_MSK1: equ E1h ; Digital PSoC block Mask Register (RW)
00E2 INT_VC: equ E2h ; Interrupt vector register (RW)
00E3 RES_WDT: equ E3h ; Watch Dog Timer (RW)
0000
0000 ; DECIMATOR Registers
00E4 DEC_DH: equ E4h ; Data Register (high byte) (RW)
00E5 DEC_DL: equ E5h ; Data Register ( low byte) (RO)
00E6 DEC_CR: equ E6h ; Data Control Register (RW)
0000
0000 ; Multiplier and MAC (Multiply/Accumulate) Unit
00E8 MUL_X: equ E8h ; Multiplier X Register (write) (WO)
00E9 MUL_Y: equ E9h ; Multiplier Y Register (write) (WO)
00EA MUL_DH: equ EAh ; Multiplier Result Data (high byte read) (RO)
00EB MUL_DL: equ EBh ; Multiplier Result Data ( low byte read) (RO)
00EC MAC_X: equ ECh ; MAC X register (write) [also see ACC_DR1](WO)
00ED MAC_Y: equ EDh ; MAC Y register (write) [also see ACC_DR0](WO)
00EE MAC_CL0: equ EEh ; MAC Clear Accum (write)[also see ACC_DR3](WO)
00EF MAC_CL1: equ EFh ; MAC Clear Accum (write)[also see ACC_DR2](WO)
00EC ACC_DR1: equ ECh ; MAC Accumulator (Read, byte 0) (RO)
00ED ACC_DR0: equ EDh ; MAC Accumulator (Read, byte 0) (RO)
00EE ACC_DR3: equ EEh ; MAC Accumulator (Read, byte 0) (RO)
00EF ACC_DR2: equ EFh ; MAC Accumulator (Read, byte 0) (RO)
0000
0000 ; Test Mode mapping of the CPU Flag (F) Register
00F7 CPU_FLAG: equ F7h ; NOTE: Only mapped when in Test Mode !!!
0000
0000
0000 ;------------------------------------------------
0000 ; System Status and Control Register
0000 ;
0000 ; Note: the following register is mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;------------------------------------------------
00FF CPU_SCR: equ FFh ; (*)
0080 CPUSCR_GIEMask: equ 80h ; MASK: flag reg Global Int Enable shadow
0020 CPUSCR_WDRSMask: equ 20h ; MASK: Watch Dog Timer Reset
0010 CPUSCR_PORSMask: equ 10h ; MASK: power-on reset bit PORS
0008 CPUSCR_SleepMask: equ 08h ; MASK: Enable Sleep
0001 CPUSCR_StopMask: equ 01h ; MASK: Halt CPU bit
0000
0000
0000 ;;===================================
0000 ;; Register Space, Bank 1
0000 ;;===================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DM0: equ 00h ; Port 0 Drive Mode 0 (WO)
0001 PRT0DM1: equ 01h ; Port 0 Drive Mode 1 (WO)
0002 PRT0IC0: equ 02h ; Port 0 Interrupt Control 0 (WO)
0003 PRT0IC1: equ 03h ; Port 0 Interrupt Control 1 (WO)
0000
0000 ; Port 1
0004 PRT1DM0: equ 04h ; Port 1 Drive Mode 0 (WO)
0005 PRT1DM1: equ 05h ; Port 1 Drive Mode 1 (WO)
0006 PRT1IC0: equ 06h ; Port 1 Interrupt Control 0 (WO)
0007 PRT1IC1: equ 07h ; Port 1 Interrupt Control 1 (WO)
0000
0000 ; Port 2
0008 PRT2DM0: equ 08h ; Port 2 Drive Mode 0 (WO)
0009 PRT2DM1: equ 09h ; Port 2 Drive Mode 1 (WO)
000A PRT2IC0: equ 0Ah ; Port 2 Interrupt Control 0 (WO)
000B PRT2IC1: equ 0Bh ; Port 2 Interrupt Control 1 (WO)
0000
0000 ; Port 3
000C PRT3DM0: equ 0Ch ; Port 3 Drive Mode 0 (WO)
000D PRT3DM1: equ 0Dh ; Port 3 Drive Mode 1 (WO)
000E PRT3IC0: equ 0Eh ; Port 3 Interrupt Control 0 (WO)
000F PRT3IC1: equ 0Fh ; Port 3 Interrupt Control 1 (WO)
0000
0000 ; Port 4
0010 PRT4DM0: equ 10h ; Port 4 Drive Mode 0 (WO)
0011 PRT4DM1: equ 11h ; Port 4 Drive Mode 1 (WO)
0012 PRT4IC0: equ 12h ; Port 4 Interrupt Control 0 (WO)
0013 PRT4IC1: equ 13h ; Port 4 Interrupt Control 1 (WO)
0000
0000 ; Port 5
0014 PRT5DM0: equ 14h ; Port 5 Drive Mode 0 (WO)
0015 PRT5DM1: equ 15h ; Port 5 Drive Mode 1 (WO)
0016 PRT5IC0: equ 16h ; Port 5 Interrupt Control 0 (WO)
0017 PRT5IC1: equ 17h ; Port 5 Interrupt Control 1 (WO)
0000
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0000 ; Digital PSoC block 0, Basic Type A
0020 DBA00FN: equ 20h ; Function Register (RW)
0021 DBA00IN: equ 21h ; Input Register (RW)
0022 DBA00OU: equ 22h ; Output Register (RW)
0000 ; (Reserved) equ 23h
0000
0000 ; Digital PSoC block 1, Basic Type A
0024 DBA01FN: equ 24h ; Function Register (RW)
0025 DBA01IN: equ 25h ; Input Register (RW)
0026 DBA01OU: equ 26h ; Output Register (RW)
0000 ; (Reserved) equ 27h
0000
0000 ; Digital PSoC block 2, Basic Type A
0028 DBA02FN: equ 28h ; Function Register (RW)
0029 DBA02IN: equ 29h ; Input Register (RW)
002A DBA02OU: equ 2Ah ; Output Register (RW)
0000 ; (Reserved) equ 2Bh
0000
0000 ; Digital PSoC block 3, Basic Type A
002C DBA03FN: equ 2Ch ; Function Register (RW)
002D DBA03IN: equ 2Dh ; Input Register (RW)
002E DBA03OU: equ 2Eh ; Output Register (RW)
0000 ; (Reserved) equ 2Fh
0000
0000 ; Digital PSoC block 4, Communications Type A
0030 DCA04FN: equ 30h ; Function Register (RW)
0031 DCA04IN: equ 31h ; Input Register (RW)
0032 DCA04OU: equ 32h ; Output Register (RW)
0000 ; (Reserved) equ 33h
0000
0000 ; Digital PSoC block 5, Communications Type A
0034 DCA05FN: equ 34h ; Function Register (RW)
0035 DCA05IN: equ 35h ; Input Register (RW)
0036 DCA05OU: equ 36h ; Output Register (RW)
0000 ; (Reserved) equ 37h
0000
0000 ; Digital PSoC block 6, Communications Type A
0038 DCA06FN: equ 38h ; Function Register (RW)
0039 DCA06IN: equ 39h ; Input Register (RW)
003A DCA06OU: equ 3Ah ; Output Register (RW)
0000 ; (Reserved) equ 3Bh
0000
0000 ; Digital PSoC block 7, Communications Type A
003C DCA07FN: equ 3Ch ; Function Register (RW)
003D DCA07IN: equ 3Dh ; Input Register (RW)
003E DCA07OU: equ 3Eh ; Output Register (RW)
0000 ; (Reserved) equ 3Fh
0000
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0060 CLK_CR0: equ 60h ; Analog Column Clock Select Register (RW)
00C0 CLK_CR0_AColumn3: equ C0h ; MASK: Specify clock for analog cloumn
0030 CLK_CR0_AColumn2: equ 30h ; MASK: Specify clock for analog cloumn
000C CLK_CR0_AColumn1: equ 0Ch ; MASK: Specify clock for analog cloumn
0003 CLK_CR0_AColumn0: equ 03h ; MASK: Specify clock for analog cloumn
0000
0061 CLK_CR1: equ 61h ; Analog Clock Source Select Register (RW)
0040 CLK_CR1_SHDIS: equ 40h ; MASK: Sample and Hold Disable (all Columns)
0038 CLK_CR1_ACLK1: equ 38h ; MASK: Digital PSoC block for analog source
0007 CLK_CR1_ACLK2: equ 07h ; MASK: Digital PSoC block for analog source
0000
0062 ABF_CR: equ 62h ; Analog Output Buffer Control Register (RW)
00C0 ABF_CR_ACI3: equ C0h ; MASK: Level 1 input mux for analog column 3
0030 ABF_CR_ACI2: equ 30h ; MASK: Level 1 input mux for analog column 2
000C ABF_CR_ACI1: equ 0Ch ; MASK: Level 1 input mux for analog column 1
0003 ABF_CR_ACI0: equ 03h ; MASK: Level 1 input mux for analog column 0
0000
0063 AMD_CR: equ 63h ; Analog Modulator Control Register (RW)
000C AMD_CR_AMOD2: equ 0Ch ; MASK: Modulation source for analog column 2
0003 AMD_CR_AMOD0: equ 03h ; MASK: Modulation source for analog column 1
0000
0000
00E0 OSC_CR0: equ E0h ; System Oscillator Control Register (RW)
0080 OSC_CR0_32K_Select: equ 80h ; MASK: Enable/Disable External XTAL Oscillator
0040 OSC_CR0_PLL_Mode: equ 40h ; MASK: Enable/Disable PLL
0018 OSC_CR0_Sleep: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_Sleep_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_Sleep_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_Sleep_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_Sleep_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System V1/V2 Divider Control Register (RW)
00F0 OSC_CR1_V1: equ F0h ; MASK System V1 24MHz divider
000F OSC_CR1_V2: equ 0Fh ; MASK System V2 24MHz divider
0000
0000 ;Reserved equ E2h
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (WO)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (WO)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (WO)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (WO)
0000
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