txc_envoy_mgmt_port_real.c

TranSwitch Envoy CE2 & Envoy CE4 设备驱动及编程指南

    /* Mask */
    regData[0].mask = 0x7;

    /* Read the registers and return the data */    
    error = TXC_BatchReg32BitRead (&batchData);
    if (error == TXC_NO_ERR)
    {
        switch (regData[0].data & 0x7)
        {
            case 0:
                mgmtPortDataPtr->mgmtClockDivideMode = ENVOY_MGMT_PORT_CLK_DIV4;
                break;

            case 1:
                mgmtPortDataPtr->mgmtClockDivideMode = ENVOY_MGMT_PORT_CLK_DIV4;
                break;


            case 2:
                mgmtPortDataPtr->mgmtClockDivideMode = ENVOY_MGMT_PORT_CLK_DIV6;
                break;

            case 3:
                mgmtPortDataPtr->mgmtClockDivideMode = ENVOY_MGMT_PORT_CLK_DIV8;
                break;

            case 4:
                mgmtPortDataPtr->mgmtClockDivideMode = ENVOY_MGMT_PORT_CLK_DIV10;
                break;

            case 5:
                mgmtPortDataPtr->mgmtClockDivideMode = ENVOY_MGMT_PORT_CLK_DIV14;
                break;

            case 6:
                mgmtPortDataPtr->mgmtClockDivideMode = ENVOY_MGMT_PORT_CLK_DIV20;
                break;

            case 7:
                mgmtPortDataPtr->mgmtClockDivideMode = ENVOY_MGMT_PORT_CLK_DIV28;
                break;

            default:
                break;
        }
    }

    return error;
}


/************************************************************************************/
/*||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||*/
/************************************************************************************

   FUNCTION:  ENVOY_PokeMacPhyRegReal

   DESCRIPTION: This function actually processess the ENVOY_PokeMacPhyReg

   INPUTS:  Same as ENVOY_PokeMacPhyReg

   RETURNS:  TXC_NO_ERR or an appropriate specific error code listed in appendix.

   CAVEATS:  None.

   REVISION HISTORY:

    Rev       Date          Author               Description
   -----    -------      ------------         -----------------
   0.5.0    6/03/04      F. Giannella         Initial release (beta)
*--------------------------------------------------------------------------*/

TXC_U16BIT ENVOY_PokeMacPhyRegReal(TXC_U16BIT handle, TXC_U16BIT phyAddr,
                                   TXC_U16BIT phyReg, TXC_U16BIT phyData)
{
    TXC_U16BIT error = TXC_NO_ERR;
    TXC_BATCH_REG_ACCESS_32BIT_STRUCT batchData;
    TXC_REG_ACCESS_32BIT_STRUCT regData[1];
    TXC_REG_32 * baseAddr;
    TXC_U16BIT phyIdx;
    TXC_U16BIT endPhy;
    TXC_U16BIT startPhy;
    TXC_U16BIT i;
    ENVOY_MGMT_PORT_STRUCT * mgmPortRegPtr;

    /* First, fill the batch platform header. This function requires 2
       registers to be written */
    memset (&regData[0], 0, (sizeof(TXC_REG_ACCESS_32BIT_STRUCT) ) );
    batchData.regDataPtr = &regData[0];
    batchData.writeVerifyFlag = TXC_WRITE_VERIFY_FLAG;
    batchData.semId = ENVOY_DbGetSemId();

    /* determine the base address of the device */
    baseAddr = (TXC_REG_32 *) ENVOY_DbGetDeviceAddr (handle);

    batchData.regCount = 1;

    /* Check if all phys are to be written or just one. */
    if (phyAddr == ENVOY_MAC_ALL_PHYS)
    {
        startPhy = 0;
        endPhy = ENVOY_MAC_MAX_PHY_ADDR + 1;
    }
    else
    {
        startPhy = phyAddr;
        endPhy = phyAddr + 1;
    }

    mgmPortRegPtr = (ENVOY_MGMT_PORT_STRUCT *) (baseAddr + ENVOY_MGMT_PORT_OFFSET);


    /* Setup the addresses to write the MAC MII Management registers */

    /* loop thru all phy addresses being written to */
    for (phyIdx = startPhy; phyIdx < endPhy; phyIdx++)
    {
        /* Setup the data and masks for the MII Mgmt address and control register*/
        regData[0].addr = (TXC_REG_32 *) &(mgmPortRegPtr->mIIMgmtAddr);
        regData[0].mask = 0x00001F1F;
        regData[0].data = ((phyIdx & 0xFF) << 8) | phyReg;
        error = TXC_BatchReg32BitWrite (&batchData);
        if (error != TXC_NO_ERR)
        {
            break;
        }
        else
        {
            /* Initiate the write cycle by writing the 16-bit write data to the MII Mgmt Write Data Register */
            regData[0].addr = (TXC_REG_32 *) &(mgmPortRegPtr->mIIMgmtDataWrite);
            regData[0].mask = 0x0000FFFF;
            regData[0].data = phyData;
            error = TXC_BatchReg32BitWrite (&batchData);
            if (error != TXC_NO_ERR)
            {
                break;
            }
            else
            {
                /* Poll the busy bit */
                i = 0;
                for (;;)
                {
                    i++;
                    regData[0].mask = 1;
                    regData[0].data = 1;
                    regData[0].addr = (TXC_REG_32 *) &(mgmPortRegPtr->mIIMgmtInd);
                    error = TXC_BatchReg32BitRead (&batchData);
                    if (!regData[0].data)
                    {
                        break;
                    }
                    if (i == 1000)
                    {
                        return error = TXC_MII_MGMT_BUSY_ERR;
                    }
                }
            }
        }
    }
    return error;
}




/************************************************************************************/
/*||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||*/
/************************************************************************************

   FUNCTION:  ENVOY_PeekMacPhyRegReal

   DESCRIPTION: This function actually processess the ENVOY_PeekMacPhyReg

   INPUTS:  Same as ENVOY_PeekMacPhyReg

   RETURNS:  TXC_NO_ERR or an appropriate specific error code listed in appendix.

   CAVEATS:  None.

   REVISION HISTORY:

    Rev       Date          Author               Description
   -----    -------      ------------         -----------------
   0.5.0    6/03/04      F. Giannella         Initial release (beta)
 *--------------------------------------------------------------------------*/

TXC_U16BIT ENVOY_PeekMacPhyRegReal(TXC_U16BIT handle, TXC_U16BIT phyAddr, 
                                   TXC_U16BIT phyReg, TXC_U16BIT * phyDataPtr)
{

    TXC_U16BIT error = TXC_NO_ERR;
    TXC_U16BIT i;
    TXC_BATCH_REG_ACCESS_32BIT_STRUCT batchData;
    TXC_REG_ACCESS_32BIT_STRUCT regData[1];
    TXC_REG_32 * baseAddr;
    ENVOY_MGMT_PORT_STRUCT * mgmPortRegPtr;

    /* First, fill the batch platform header. This function requires 1
       register to be read */
    memset (&regData, 0, sizeof(TXC_REG_ACCESS_32BIT_STRUCT) );
    batchData.regDataPtr = &regData[0];
    batchData.writeVerifyFlag = TXC_WRITE_VERIFY_FLAG;
    batchData.semId = TXC_FALSE;
    batchData.regCount = 1;

    /* determine the base address of the device */
    baseAddr = (TXC_REG_32 *) ENVOY_DbGetDeviceAddr (handle);

    mgmPortRegPtr = (ENVOY_MGMT_PORT_STRUCT *) (baseAddr + ENVOY_MGMT_PORT_OFFSET);

    /* Setup the address to access the MAC MII Management Phy and register */
    regData[0].addr = (TXC_REG_32 *) &(mgmPortRegPtr->mIIMgmtAddr);
    regData[0].mask = 0x00001F1F;
    regData[0].data = ((phyAddr & 0xFF) << 8) | phyReg;
    error = TXC_BatchReg32BitWrite (&batchData);

    if (error == TXC_NO_ERR)
    {
        /* Initiate the READ cycle by clearing the "read bit" in MII MGMT Command Register */
        regData[0].addr = (TXC_REG_32 *) &(mgmPortRegPtr->mIIMgmtCmd);
        regData[0].mask = 3;
        regData[0].data = 0; /* no scan mode enabled */
        error = TXC_BatchReg32BitWrite (&batchData);
        if (error == TXC_NO_ERR)
        {
            /* Initiate the READ cycle by setting the "read bit" in MII MGMT Command Register */
            regData[0].data = 1; /* no scan mode enabled */
            error = TXC_BatchReg32BitWrite (&batchData);

            if (error == TXC_NO_ERR)
            {
                /* If the address was written properly, then read the data */
                i = 0;
                for (;;)
                {
                    i++;
                    /* Poll the busy bit in MII Mgmt Read Data Register */
                    regData[0].addr = (TXC_REG_32 *) &(mgmPortRegPtr->mIIMgmtDataRead);
                    regData[0].mask = 0x8000FFFF;
                    error = TXC_BatchReg32BitRead (&batchData);
                    if ((regData[0].data & 0x80000000) == 0)
                    {
                        break;
                    }
                    if (i == 1000)
                    {
                        error = TXC_MII_MGMT_BUSY_ERR;
                        break;
                    }
                }
                /* Isolate the data */
                *phyDataPtr = regData[0].data & 0xFFFF;

                /* Finalize the READ cycle by clearing the "read bit" in MII MGMT Command Register */
                regData[0].addr = (TXC_REG_32 *) &(mgmPortRegPtr->mIIMgmtCmd);
                regData[0].mask = 3;
                regData[0].data = 0; /* no scan mode enabled */
                error = TXC_BatchReg32BitWrite (&batchData);
            }
        }
    }
    return error;
}

#endif /* ENVOY_VIRTUAL_DEVICE_MODE */


/****************************************************************************
 **                              End of Module                             **
 ****************************************************************************/