📄 txc_envoy_mem_map.h
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}ENVOY_OSPI_AGGR_TAG_STRUCT;
/* End of SPI-3 OUTPUT Interface Reg map */
/*********************************************************************
=== Envoy-CE2/CE4 EGRESS FIFO Block Reg map
**********************************************************************/
/* Offset for the 32 (one per port) Packet Drop Counters of the Egress FIFO Block */
#define ENVOY_EFIFO_PORT_CNT_OFFSET 0x900 /* 0x2400 : 0x900 */
typedef struct _tagENVOY_EFIFO_PORT_CNT_STRUCT
{
TXC_REG_32 eFifoPortCntReg[ENVOY_CE4_NUM_MACS];
}ENVOY_EFIFO_PORT_CNT_STRUCT;
/* Global (all ports) status registers of Egress FIFO Block */
#define ENVOY_EFIFO_STATUS_OFFSET 0x940 /* 0x2500 : 0x940 */
typedef struct _tagENVOY_EFIFO_STATUS_STRUCT
{
TXC_REG_32 eFifoFullStatusReg; /* 0x2500 : 0x940 */
TXC_REG_32 eFifoDisabledErrStatusReg; /* 0x2504 : 0x941 */
TXC_REG_32 eFifoSopErrStatusReg; /* 0x2508 : 0x942 */
}ENVOY_EFIFO_STATUS_STRUCT;
/* Mode configuration register of Egress FIFO Block */
#define ENVOY_EFIFO_MODE_OFFSET 0x950 /* 0x2540 : 0x950 */
typedef struct _tagENVOY_EFIFO_MODE_STRUCT
{
TXC_REG_32 eFifoModeReg;
}ENVOY_EFIFO_MODE_STRUCT;
/* Egress FIFO Interrupt Handler Registers */
#define ENVOY_EFIFO_INT_HDLR_OFFSET 0x951 /* 0x2544 : 0x951 */
typedef struct _tagENVOY_EFIFO_INT_HDLR_STRUCT
{
TXC_REG_32 eFifoFullInterrupMaskReg; /* 0x2544 : 0x951 */
TXC_REG_32 eFifoDisabledErrInterrupMaskReg; /* 0x2548 : 0x952 */
TXC_REG_32 eFifoSopErrInterrupMaskReg; /* 0x254C : 0x953 */
}ENVOY_EFIFO_INT_HDLR_STRUCT;
/* Port Enable register of Egress FIFO Block */
#define ENVOY_EFIFO_PORT_CTRL_OFFSET 0x954 /* 0x2550 : 0x954 */
typedef struct _tagENVOY_EFIFO_PORT_CTRL_STRUCT
{
TXC_REG_32 eFifoPortCtrlReg;
}ENVOY_EFIFO_PORT_CTRL_STRUCT;
/* Offset for the 32 (one per port) streaming threshold registers */
#define ENVOY_EFIFO_PORT_STRM_THRSHLD_OFFSET 0x960 /* 0x2580 : 0x960 */
typedef struct _tagENVOY_EFIFO_PORT_STRM_THRSHLD_STRUCT
{
TXC_REG_32 eFifoPortStreamThrshldReg[ENVOY_CE4_NUM_MACS];
}ENVOY_EFIFO_PORT_STRM_THRSHLD_STRUCT;
/* End of EGRESS FIFO Block Reg map */
/*********************************************************************
=== Envoy-CE2/CE4 INGRESS FIFO Block Reg map
**********************************************************************/
/* Offset for the 32 (one per port) Packet Drop Counters of the Ingress FIFO Block */
#define ENVOY_IFIFO_PORT_CNT_OFFSET 0x980 /* 0x2600 : 0x980 */
typedef struct _tagENVOY_IFIFO_PORT_CNT_STRUCT
{
TXC_REG_32 iFifoPortCntReg[ENVOY_CE4_NUM_MACS];
}ENVOY_IFIFO_PORT_CNT_STRUCT;
/* Global (all ports) status registers of Ingress FIFO Block */
#define ENVOY_IFIFO_STATUS_OFFSET 0x9C0 /* 0x2700 : 0x9C0 */
typedef struct _tagENVOY_IFIFO_STATUS_STRUCT
{
TXC_REG_32 iFifoFullStatusReg; /* 0x2700 : 0x9C0 */
TXC_REG_32 iFifoNearFullStatusReg; /* 0x2704 : 0x9C1 */
}ENVOY_IFIFO_STATUS_STRUCT;
/* Mode configuration register of Egress FIFO Block */
#define ENVOY_IFIFO_MODE_OFFSET 0x9E0 /* 0x2780 : 0x9E0 */
typedef struct _tagENVOY_IFIFO_MODE_STRUCT
{
TXC_REG_32 iFifoModeReg;
}ENVOY_IFIFO_MODE_STRUCT;
/* Ingress FIFO Loopback Mode Registers */
#define ENVOY_IFIFO_LOOPBACK_OFFSET 0x9E1 /* 0x2784 : 0x9E1 */
typedef struct _tagENVOY_IFIFO_LOOPBACK_STRUCT
{
TXC_REG_32 iFifoLbkEnableReg; /* 0x2784 : 0x9E1 */
TXC_REG_32 iFifoNonTransparentLbkEnableReg; /* 0x2788 : 0x9E2 */
}ENVOY_IFIFO_LOOPBACK_STRUCT;
/* Offset for the two (High and Low) Ingress Traffic Flow Control threshold
registers (two registers per CMAC, an octal port block).
The CMAC Id (0, 1, 2, 3) will be used to access the proper threshold pair */
/*
#define ENVOY_IFIFO_FC_THRSHLD_OFFSET 0x9E3 */ /* 0x278C : 0x9E3 */
/*
typedef struct _tagENVOY_IFIFO_CMAC_FC_THRSHLD_STRUCT
{
TXC_REG_32 iFifoCmacFcHiThrshldReg[ENVOY_MAX_NUM_CMACS];
TXC_REG_32 iFifoCmacFcLoThrshldReg[ENVOY_MAX_NUM_CMACS];
}ENVOY_IFIFO_CMAC_FC_THRSHLD_STRUCT;
*/
extern TXC_REG_32 iFifoCmacFcOffset[]; /* ENVOY_IFIFO_CMAC_FC_THRSHLD_STRUCT offsets */
/*#define ENVOY_IFIFO_FC_THRSHLD_OFFSET 0x9E3 */ /* 0x278C : 0x9E3 */
typedef struct _tagENVOY_IFIFO_CMAC_FC_THRSHLD_STRUCT
{
TXC_REG_32 iFifoCmacFcHiThrshldReg;
TXC_REG_32 iFifoCmacFcLoThrshldReg;
}ENVOY_IFIFO_CMAC_FC_THRSHLD_STRUCT;
/* Offset for the 4 PAUSE Frame Regeneration Timer registers (one per CMAC) */
#define ENVOY_IFIFO_PAUSE_TIMER_OFFSET 0x9EB /* 0x27AC : 0x9EB */
typedef struct _tagENVOY_IFIFO_CMAC_PF_TIMER_STRUCT
{
TXC_REG_32 iFifoCmacPfTimerReg[ENVOY_MAX_NUM_CMACS];
}ENVOY_IFIFO_CMAC_PF_TIMER_STRUCT;
/* Ingress FIFO Interrupt Handler Registers */
#define ENVOY_IFIFO_INT_HDLR_OFFSET 0x9EF /* 0x27BC : 0x9EF */
typedef struct _tagENVOY_IFIFO_INT_HDLR_STRUCT
{
TXC_REG_32 iFifoFullInterrupMaskReg; /* 0x27BC : 0x9EF */
TXC_REG_32 iFifoNearFullInterrupMaskReg; /* 0x27C0 : 0x9F0 */
}ENVOY_IFIFO_INT_HDLR_STRUCT;
/* Port Enable register of Ingress FIFO Block */
#define ENVOY_IFIFO_PORT_CTRL_OFFSET 0x9F1 /* 0x27C4 : 0x9F1 */
typedef struct _tagENVOY_IFIFO_PORT_CTRL_STRUCT
{
TXC_REG_32 iFifoPortCtrlReg;
}ENVOY_IFIFO_PORT_CTRL_STRUCT;
/* End of EGRESS FIFO Block Reg map */
/*********************************************************************
=== Envoy-CE2/CE4 EIB (Ethernet Interface Block) Reg map
Note 1: This block includes the MAC core, the Interface (Ethernet ports)
and the Packet Controller.
Note 2: Only byte offsets are given in "comments" of the structures below.
The 32-bit offsets associated each structure per port is given in
txc_envoy_mem_map.c.
**********************************************************************/
/* The per-port offsets (macCfgOffset[]) are defined in txc_envoy_mem_map.c */
/* Global Address Constant: */
extern TXC_REG_32 macCfgOffset[]; /* ENVOY_MAC_CONFIG_STRUCT offsets */
typedef struct _tagENVOY_MAC_CFG_STRUCT
{ /* Byte offsets */
/* MAC 0 1 . 31 */
TXC_REG_32 cfg1Reg; /* 0x4000, 0x4100, ....... 0x5F00 */
TXC_REG_32 cfg2Reg; /* 0x4004, 0x4104, ......... 0x5F04 */
TXC_REG_32 ipgIfgReg; /* 0x4008, 0x4108, ......... 0x5F08 */
TXC_REG_32 halfDplxReg; /* 0x400C, 0x410C, ......... 0x5F0C */
TXC_REG_32 maxFrmLenReg; /* 0x4010, 0x4110, ......... 0x5F10 */
TXC_REG_32 rsvd1Reg;
TXC_REG_32 rsvd2Reg;
TXC_REG_32 testReg; /* 0x401C, 0x411C, ......... 0x5F1C */
TXC_REG_32 rsvd3Reg;
TXC_REG_32 rsvd4Reg;
TXC_REG_32 rsvd5Reg;
TXC_REG_32 rsvd6Reg;
TXC_REG_32 rsvd7Reg;
TXC_REG_32 rsvd8Reg;
TXC_REG_32 ifaceCtrlReg; /* 0x4038, 0x4138, ......... 0x5F38 */
TXC_REG_32 ifaceStatusReg; /* 0x403C, 0x413C, ......... 0x5F3C */
TXC_REG_32 stationAddr1Reg; /* 0x4040, 0x4140, ......... 0x5F40 */
TXC_REG_32 stationAddr2Reg; /* 0x4044, 0x4144, ......... 0x5F44 */
}ENVOY_MAC_CONFIG_STRUCT;
/* Per-port offsets (macPktCtrlOffset[]): defined in txc_envoy_mem_map.c */
/* Global Address Constant: */
extern TXC_REG_32 macPktCtrlOffset[]; /* ENVOY_MAC_PKT_CTRL_STRUCT */
typedef struct _tagENVOY_MAC_PKT_CTRL_STRUCT
{ /* MAC 0 1 - 31 */
TXC_REG_32 cfptCfepReg; /* 0x4080, 0x4180, ....... 0x5F80 */
TXC_REG_32 frameCtrlReg; /* 0x4084, 0x4184, ....... 0x5F84 */
TXC_REG_32 frameStatusReg; /* 0x4088, 0x4188, ....... 0x5F88 */
TXC_REG_32 portModeStatusReg; /* 0x408C, 0x418C, ....... 0x5F8C */
}ENVOY_MAC_PKT_CTRL_STRUCT;
/* Note: the Global Address Constants macRxCntOffset []
are defined in: txc_envoy_mem_map.c*/
extern TXC_REG_32 macRxCntOffset[]; /* offsets to ENVOY_MAC_RX_RMON_STRUCT */
typedef struct _tagENVOY_MAC_RX_RMON_STRUCT
{ /* MAC 0 1 - 31 */
TXC_U32BIT rbytloCntReg; /* 0x6000, 0x6100, ....... 0x7F00 */
TXC_U32BIT rpktCntReg; /* 0x6004, 0x6104, ....... 0x7F04 */
TXC_U32BIT rundCntReg; /* 0x6008, 0x6108, ....... 0x7F08 */
TXC_U32BIT rx64CntReg; /* 0x600C, 0x610C, ....... 0x7F0C */
TXC_U32BIT r127CntReg; /* 0x6010, 0x6110, ....... 0x7F10 */
TXC_U32BIT r255CntReg; /* 0x6014, 0x6114, ....... 0x7F14 */
TXC_U32BIT r511CntReg; /* 0x6018, 0x6118, ....... 0x7F18 */
TXC_U32BIT r1023CntReg; /* 0x601C, 0x611C, ....... 0x7F1C */
TXC_U32BIT r1518CntReg; /* 0x6020, 0x6120, ....... 0x7F20 */
TXC_U32BIT rflrCntReg; /* 0x6024, 0x6124, ....... 0x7F24 */
TXC_U32BIT rovrCntReg; /* 0x6028, 0x6128, ....... 0x7F28 */
TXC_U32BIT rbcaCntReg; /* 0x602C, 0x612C, ....... 0x7F2C */
TXC_U32BIT rmcaCntReg; /* 0x6030, 0x6130, ....... 0x7F30 */
TXC_U32BIT rpfCntReg; /* 0x6034, 0x6134, ....... 0x7F34 */
TXC_U32BIT ruoCntReg; /* 0x6038, 0x6138, ....... 0x7F38 */
TXC_U32BIT rvlnCntReg; /* 0x603C, 0x613C, ....... 0x7F3C */
TXC_U32BIT rfrgCntReg; /* 0x6040, 0x6140, ....... 0x7F40 */
TXC_U32BIT rfcsCntReg; /* 0x6044, 0x6144, ....... 0x7F44 */
TXC_U32BIT rjbrCntReg; /* 0x6048, 0x6148, ....... 0x7F48 */
TXC_U32BIT rcdeCntReg; /* 0x604C, 0x614C, ....... 0x7F4C */
TXC_U32BIT rdfffCntReg; /* 0x6050, 0x6150, ....... 0x7F50 */
TXC_U32BIT rdfucCntReg; /* 0x6054, 0x6154, ....... 0x7F54 */
}ENVOY_MAC_RX_RMON_STRUCT;
/* Note: the Global Address Constants macTxCntOffset []
are defined in: txc_envoy_mem_map.c*/
extern TXC_REG_32 macTxCntOffset[]; /* offsets to ENVOY_MAC_TX_RMON_STRUCT */
typedef struct _tagENVOY_MAC_TX_RMON_STRUCT
{ /* MAC 0 1 - 31 */
TXC_U32BIT tbytloCntReg; /* 0x6058, 0x6158, ....... 0x7F58 */
TXC_U32BIT tpktCntReg; /* 0x605C, 0x615C, ....... 0x7F5C */
TXC_U32BIT tundCntReg; /* 0x6060, 0x6160, ....... 0x7F60 */
TXC_U32BIT t64CntReg; /* 0x6064, 0x6164, ....... 0x7F64 */
TXC_U32BIT t127CntReg; /* 0x6068, 0x6168, ....... 0x7F68 */
TXC_U32BIT t255CntReg; /* 0x606C, 0x616C, ....... 0x7F6C */
TXC_U32BIT t511CntReg; /* 0x6070, 0x6170, ....... 0x7F70 */
TXC_U32BIT t1023CntReg; /* 0x6074, 0x6174, ....... 0x7F74 */
TXC_U32BIT t1518CntReg; /* 0x6078, 0x6178, ....... 0x7F78 */
TXC_U32BIT tpfdCntReg; /* 0x607C, 0x617C, ....... 0x7F7C */
TXC_U32BIT tovrCntReg; /* 0x6080, 0x6180, ....... 0x7F80 */
TXC_U32BIT tbcaCntReg; /* 0x6084, 0x6184, ....... 0x7F84 */
TXC_U32BIT tmcaCntReg; /* 0x6088, 0x6188, ....... 0x7F88 */
TXC_U32BIT tpfCntReg; /* 0x608C, 0x618C, ....... 0x7F8C */
TXC_U32BIT tvlnCntReg; /* 0x6090, 0x6190, ....... 0x7F90 */
TXC_U32BIT tdfrCntReg; /* 0x6094, 0x6194, ....... 0x7F94 */
TXC_U32BIT tedfCntReg; /* 0x6098, 0x6198, ....... 0x7F98 */
TXC_U32BIT tsclCntReg; /* 0x609C, 0x619C, ....... 0x7F9C */
TXC_U32BIT tmclCntReg; /* 0x60A0, 0x61A0, ....... 0x7FA0 */
TXC_U32BIT tlclCntReg; /* 0x60A4, 0x61A4, ....... 0x7FA4 */
TXC_U32BIT texclCntReg; /* 0x60A8, 0x61A8, ....... 0x7FA8 */
TXC_U32BIT tfrgCntReg; /* 0x60AC, 0x61AC, ....... 0x7FAC */
TXC_U32BIT tfcsCntReg; /* 0x60B0, 0x61B0, ....... 0x7FB0 */
TXC_U32BIT tjbrCntReg; /* 0x60B4, 0x61B4, ....... 0x7FB4 */
TXC_U32BIT tdrpCntReg; /* 0x60B8, 0x61B8, ....... 0x7FB8 */
TXC_U32BIT tabtCntReg; /* 0x60BC, 0x61BC, ....... 0x7FBC */
TXC_U32BIT rbythiCntReg; /* 0x60C0, 0x61C0, ....... 0x7FC0 */
TXC_U32BIT tbythiCntReg; /* 0x60C4, 0x61C4, ....... 0x7FC4 */
}ENVOY_MAC_TX_RMON_STRUCT;
/* End of EIB (Ethernet Interface Block) Reg map */
#endif /* TXC_ENVOY_MEM_MAP_H */⌨️ 快捷键说明
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