📄 txc_envoy_mem_map.h
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/*--------------------------------------------------------------------------
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* ***** ** * * * * * * ***** **** * *
* * * * * ** * * * * * * * * * *
* * * * * * * * **** * * * * * ******
* ***** ****** * * * * * ** * * * * * *
* * * * * * ** * * ** ** * * * * * *
* * * * * * * **** * * * * **** * *
Proprietary and Confidential
This program is made available only to customers and prospective customers
of TranSwitch Corporation under license and may be used only with TranSwitch
semi-conductor products.
Copyright(c) 2004 TranSwitch Inc.
--------------------------------------------------------------------------
******* ** ** ** ** ******** ** **
******* *** ** ** ** ********** ** **
** ** * ** ** ** ** ** ** **
***** ** * ** ** ** ** ** * *
***** ** * ** ** ** ** ** **
** ** * ** ** ** ** ** **
******* ** *** **** ********** **
******* ** ** ** ******** **
--------------------------------------------------------------------------
TranSwitch Envoy-CE2/CE4
Device Driver
--------------------------------------------------------------------------
Workfile: txc_envoy_mem_map.h
Description: Register Mapped constants and structures for the
Envoy-CE2/CE4 device.
--------------------------------------------------------------------------
Revision History
--------------------------------------------------------------------------
Rev # Date Author Description
----- ------- ----------- -----------
0.5.0 6/03/04 F. Giannella Initial release (beta)
*--------------------------------------------------------------------------*/
#ifndef TXC_ENVOY_MEM_MAP_H
#define TXC_ENVOY_MEM_MAP_H
/*********************************************************************
* ENVOY CE2/CE4 DEFINES *
*********************************************************************/
#define ENVOY_CE2_NUM_MACS 16
#define ENVOY_CE4_NUM_MACS 32
#define ENVOY_MAX_NUM_CMACS 4
/* Offsets to the start of memory map structures */
/* Offsets are in 32-bit word units */
/* The defines below are used to initialize
the counters during device reset */
#define ENVOY_RMON_PORT_REG_OFFSET 0x0100 /* offset from consecutive ports */
#define ENVOY_EIB0_1STCNT_OFFSET 0x1800
#define ENVOY_EIB0_LASTCNT_OFFSET 0x1831
#define ENVOY_ISPI0_1STCNT_OFFSET (ENVOY_ISPI_GLBL_CNT_OFFSET)
#define ENVOY_ISPI0_LASTERR_OFFSET 0x083F
#define ENVOY_EFIFO_1STCNT_OFFSET (ENVOY_EFIFO_PORT_CNT_OFFSET)
#define ENVOY_EFIFO_LASTCNT_OFFSET 0x091F
#define ENVOY_IFIFO_1STCNT_OFFSET (ENVOY_IFIFO_CNT_OFFSET)
#define ENVOY_IFIFO_LASTCNT_OFFSET 0x099F
/*********************************************************************
* ENVOY CE4 REGISTER MAP *
Note 1: Envoy CE2 register map applies to ports in the range of
0 to 15, therefore, a subset of Envoy-CE4 register map (port
range of 0 to 31).
Note 2: The Register offset addresses in this file have been defined
based on Envoy Data Sheet TXC-06885-MB, Ed 1A, February 2004.
Note 3: All addresses herein are 32-bit word addressable. Therefore,
in order to determine the associated byte-word addresses
encountered in the Data Sheet, one has to multiply them by 4.
Say, the ENVOY_HOST_RESET_OFFSET below (4) corresponds to
register offset 0x10 in the Data Sheet.
*********************************************************************/
/*********************************************************************
=== Envoy-CE2/CE4 HOST Interface Reg map
**********************************************************************/
/* OFFSET
in byte : in 32-bit
units word units */
/* Note: it is assummed that the offset
associated with the structure below is 0 */
typedef struct _tagENVOY_ID_REGISTER_STRUCT
{
TXC_REG_32 deviceId; /* 0x0000 : 0 */
}ENVOY_ID_REGISTER_STRUCT;
#define ENVOY_HOST_RSV_OFFSET 1 /* 0x0004 : 1 */
typedef struct _tagENVOY_HOST_RSV_STRUCT
{
TXC_REG_32 rsv1; /* 0x0004 : 1 */
TXC_REG_32 scratchReg; /* 0x0008 : 2 */
TXC_REG_32 rsv2; /* 0x000C : 3 */
}ENVOY_HOST_RSV_STRUCT;
/* Host I/F Reset Registers */
#define ENVOY_HOST_RESET_OFFSET 4 /* 0x0010 : 4 */
typedef struct _tagENVOY_HOST_RESET_STRUCT
{
TXC_REG_32 resetEthernetPortReg; /* 0x0010 : 4 */
TXC_REG_32 resetModuleReg; /* 0x0014 : 5 */
}ENVOY_HOST_RESET_STRUCT;
/* Host I/F Interrupt Handler Registers */
#define ENVOY_HOST_INT_HDLR_OFFSET 6 /* 0x0018 : 6 */
typedef struct _tagENVOY_HOST_INT_HDLR_STRUCT
{
TXC_REG_32 interruptMaskPortReg; /* 0x0018 : 6 */
TXC_REG_32 interruptMaskModuleReg; /* 0x001C : 7 */
TXC_REG_32 interruptStatusPortReg; /* 0x0020 : 8 */
TXC_REG_32 interruptStatusModuleReg; /* 0x0024 : 9 */
}ENVOY_HOST_INT_HDLR_STRUCT;
/* Host I/F PIN Status Register */
#define ENVOY_HOST_PIN_OFFSET 0xA /* 0x0028 : 0xA */
typedef struct _tagENVOY_HOST_PIN_RMONCTRL_STRUCT
{
TXC_REG_32 pinReg; /* 0x0028 : 0xA */
TXC_REG_32 rsv1; /* 0x002C : 0xB */
TXC_REG_32 rmonCtrlReg; /* 0x0030 : 0xC */
}ENVOY_HOST_PIN_RMONCTRL_STRUCT;
/* Host I/F Port Interrupt Handler Registers */
#define ENVOY_HOST_STATS_INT_HDLR_OFFSET 0xD /* 0x0034 : 0xD */
typedef struct _tagHOST_STATS_INT_HDLR_STRUCT
{
TXC_REG_32 interruptStatusPortStatsReg; /* 0x0034 : 0xD */
TXC_REG_32 interruptMaskPortStatsReg; /* 0x0038 : 0xE */
TXC_REG_32 rsv1; /* 0x003C : 0xF */
}ENVOY_HOST_STATS_INT_HDLR_STRUCT;
/* END of HOST Interface Reg Map */
/*********************************************************************
=== Envoy-CE2/CE4 MANAGEMENT MII Interface Reg map
Note: Although physically implemented as a sub-block of the Host I/F,
the Management Port is a separate interface on its own.
**********************************************************************/
/* Management Port Interface */
#define ENVOY_MGMT_PORT_OFFSET 0x10 /* 0x0040 : 0x10 */
typedef struct _tagENVOY_MGMT_PORT_STRUCT
{
TXC_REG_32 mIIMgmtCfg; /* 0x0040 : 0x10 note: bit 6 is new */
TXC_REG_32 mIIMgmtCmd; /* 0x0044 : 0x11 */
TXC_REG_32 mIIMgmtAddr; /* 0x0048 : 0x12 */
TXC_REG_32 mIIMgmtDataWrite; /* 0x004C : 0x13 */
TXC_REG_32 mIIMgmtDataRead; /* 0x0050 : 0x14 */
TXC_REG_32 mIIMgmtInd; /* 0x0054 : 0x15 */
}ENVOY_MGMT_PORT_STRUCT;
/* END of Management Port Interface Memory Map */
/*********************************************************************
=== Envoy-CE2/CE4 SPI-3 INPUT Interface Reg map
**********************************************************************/
/* Configuration registers of SPI-3 Input I/F */
#define ENVOY_ISPI_CFG_OFFSET 0x0800 /* 0x2000 : 0x800 */
typedef struct _tagENVOY_ISPI_CFG_STRUCT
{
TXC_REG_32 iSpi3CfgReg; /* 0x2000 : 0x800 */
TXC_REG_32 iSpi3PortEnableReg; /* 0x2004 : 0x801 */
TXC_REG_32 iSpi3StpaHiReg; /* 0x2008 : 0x802 */
TXC_REG_32 iSpi3StpaLoReg; /* 0x200C : 0x803 */
TXC_REG_32 iSpi3PtpaHiReg; /* 0x2010 : 0x804 */
TXC_REG_32 iSpi3PtpaLoReg; /* 0x2014 : 0x805 */
TXC_REG_32 iSpi3StpaPoliceEnableReg; /* 0x2018 : 0x806 */
TXC_REG_32 rsv1; /* 0x201C : 0x807 */
}ENVOY_ISPI_CFG_STRUCT;
/* Global status register of SPI-3 Input I/F */
#define ENVOY_ISPI_GLBL_STATUS_OFFSET 0x810 /* 0x2040 : 0x810 */
typedef struct _tagENVOY_ISPI_GLBL_STATUS_STRUCT
{
TXC_REG_32 iSpi3StatusReg; /* 0x2040 : 0x810 */
}ENVOY_ISPI_GLBL_STATUS_STRUCT;
/* Global status interrupt mask register of SPI-3 Input I/F */
#define ENVOY_ISPI_STATUS_INT_MASK_OFFSET 0x814 /* 0x2050 : 0x814 */
typedef struct _tagENVOY_ISPI_STATUS_INT_MASK_STRUCT
{
TXC_REG_32 iSpi3StatusIntMaskReg; /* 0x0000 : 0 */
}ENVOY_ISPI_STATUS_INT_MASK_STRUCT;
/* Global counter registers of SPI-3 Input I/F */
#define ENVOY_ISPI_GLBL_CNT_OFFSET 0x818 /* 0x2060 : 0x818 */
typedef struct _tagENVOY_ISPI_GLBL_CNT_STRUCT
{
TXC_REG_32 iSpi3GlblParErrCntReg; /* 0x2060 : 0x818 */
TXC_REG_32 iSpi3GlblSopErrCntReg; /* 0x2064 : 0x819 */
TXC_REG_32 iSpi3GlblDiscardCntReg; /* 0x2068 : 0x81A */
}ENVOY_ISPI_GLBL_CNT_STRUCT;
/* Offset for the 32 (one per port) packet error counters */
#define ENVOY_ISPI_PER_PORT_CNT_OFFSET 0x820 /* 0x2080 : 0x820 */
typedef struct _tagENVOY_ISPI_PORT_CNT_STRUCT
{
TXC_REG_32 iSpi3PktErrPortCntReg[ENVOY_CE4_NUM_MACS]; /* 0x2080 : 0x820 */
}ENVOY_ISPI_PORT_CNT_STRUCT;
/* End of SPI-3 INPUT Interface Reg map */
/*********************************************************************
=== Envoy-CE2/CE4 SPI-3 OUTPUT Interface Reg map
**********************************************************************/
/* Configuration registers of SPI-3 Output I/F */
#define ENVOY_OSPI_CFG_OFFSET 0x880 /* 0x2200 : 0x880 */
typedef struct _tagENVOY_OSPI_CFG_STRUCT
{
TXC_REG_32 oSpi3CfgReg; /* 0x2200 : 0x880 */
TXC_REG_32 oSpi3PortEnableReg; /* 0x2204 : 0x881 */
TXC_REG_32 oSpi3NearFullReg; /* 0x2208 : 0x882 */
TXC_REG_32 oSpi3BurstSizeReg; /* 0x220C : 0x883 */
TXC_REG_32 oSpi3StpaEnableReg; /* 0x2210 : 0x884 */
TXC_REG_32 oSpi3PtpaEnableReg; /* 0x2214 : 0x885 */
}ENVOY_OSPI_CFG_STRUCT;
/* Offset for the 32 (one per port) aggregation tag registers */
#define ENVOY_OSPI_AGGR_TAG_OFFSET 0x8A0 /* 0x2280 : 0x8A0 */
typedef struct _tagENVOY_OSPI_AGGR_TAG_STRUCT
{
TXC_REG_32 oSpi3PortAggrTagReg[ENVOY_CE4_NUM_MACS];
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