txc_envoy_spi3_real.c

TranSwitch Envoy CE2 & Envoy CE4 设备驱动及编程指南

    regData[0].mask = (OSPI_REG_2200_MASK | OSPI_PARITY_MODE_MASK);
    regData[1].mask = OSPI_REG_2210_MASK;
    regData[2].mask = OSPI_REG_2214_MASK;

    /* Read the registers and return the data */

    /* INTERFACE MODE */
    error = TXC_BatchReg32BitRead (&batchData);
    if (error == TXC_NO_ERR)
    {
        error = TXC_ENVOY_DeviceExPinRtrv (handle, &pinData);
        if (error != TXC_NO_ERR)
        {
            return error;
        }
        else
        {
            tempData = (regData[0].data >> 5 ) & 0x1;
            if ((tempData == 0x1) && (pinData.spi3OutputMode == ENVOY_DEV_PIN_SPI3_PHY_MODE))
            {
                spi3OutputIfaceDataPtr->outputMode = TXC_IfSPI3_PHY_LAYER_SINGLE_PHY;
            }
            else if ((tempData == 0x0) && (pinData.spi3OutputMode == ENVOY_DEV_PIN_SPI3_PHY_MODE))
            {
                spi3OutputIfaceDataPtr->outputMode = TXC_IfSPI3_PHY_LAYER_MULTI_PHY;
            }
            else if ((tempData == 0x1) && (pinData.spi3OutputMode == ENVOY_DEV_PIN_SPI3_LINK_MODE))
            {
                spi3OutputIfaceDataPtr->outputMode = TXC_IfSPI3_LINK_LAYER_SINGLE_PHY;
            }
            else
            {
                spi3OutputIfaceDataPtr->outputMode = TXC_IfSPI3_LINK_LAYER_MULTI_PHY;
            }
        }
    }

    /* Return pi-configurable BUS WIDTH parameter */
    switch (pinData.spi3WidthMode)
    {
        case ENVOY_DEV_PIN_SPI3_32_BITS:
            spi3OutputIfaceDataPtr->outputBusWidth = TXC_IfSPI3_BUS_WIDTH_32BIT;
            break;

        case ENVOY_DEV_PIN_SPI3_16_BITS:
            spi3OutputIfaceDataPtr->outputBusWidth = TXC_IfSPI3_BUS_WIDTH_16BIT;
            break;

        case ENVOY_DEV_PIN_SPI3_8_BITS:
            spi3OutputIfaceDataPtr->outputBusWidth = TXC_IfSPI3_BUS_WIDTH_8BIT;
            break;

        default:
            spi3OutputIfaceDataPtr->outputBusWidth = TXC_IfSPI3_BUS_WIDTH_NONE;
            break;
    }

    /* PARITY MODE */
    tempData = (regData[0].data >> 7) & 0x3;
    if (tempData & 0x2)  /* that is, if parity checking is enabled */
    {
        if (tempData == 0x2)
        {
            spi3OutputIfaceDataPtr->outputParityGenerationMode = TXC_IfSPI3_EVEN_PARITY;
        }
        else
        {
            spi3OutputIfaceDataPtr->outputParityGenerationMode = TXC_IfSPI3_ODD_PARITY;
        }
    }
    else
    {
        spi3OutputIfaceDataPtr->outputParityGenerationMode = TXC_IfSPI3_NO_PARITY;
    }

    /* FLOW CONTROL */
    ptpaStpa = regData[1].data & 0x1;
    ptpaStpa |= (regData[2].data & 0x1) << 1;
    switch (ptpaStpa)
    {
        case 0:  
            spi3OutputIfaceDataPtr->outputFlowControlMode = TXC_IfSPI3_OUTPUT_FLOW_CONTROL_NONE;
            break;

        case 1:
            spi3OutputIfaceDataPtr->outputFlowControlMode = TXC_IfSPI3_OUTPUT_FLOW_CONTROL_STPA;
            break;

        case 2:
            spi3OutputIfaceDataPtr->outputFlowControlMode = TXC_IfSPI3_OUTPUT_FLOW_CONTROL_PTPA;
            break;

        case 3:
            spi3OutputIfaceDataPtr->outputFlowControlMode = TXC_IfSPI3_OUTPUT_FLOW_CONTROL_STPA_PTPA;
            break;

        default:
            return error = TXC_GEN_ERR;  /* added so that lint will be happy */
            break;
    }

    /* PAUSE CYCLE TIMER */
    tempData = (regData[0].data >> 4) & 0x1;
    if (tempData)
    {
        spi3OutputIfaceDataPtr->outputPauseTimerMode = TXC_IfSPI3_OUTPUT_PAUSE_2_CYCLE;
    }
    else
    {
        spi3OutputIfaceDataPtr->outputPauseTimerMode = TXC_IfSPI3_OUTPUT_PAUSE_0_CYCLE;
    }

    /* AGGREGATION MODE */
    tempData = (regData[0].data >> 6) & 0x1;
    if (tempData)
    {
        spi3OutputIfaceDataPtr->outputDeviceExtension.envoyCe2Ce4OutputAttr.outputAggregationEnable = TXC_TRUE;
    }
    else
    {
        spi3OutputIfaceDataPtr->outputDeviceExtension.envoyCe2Ce4OutputAttr.outputAggregationEnable = TXC_FALSE;
    }

    /* BASE ADDRESS */
    tempData = regData[0].data & 0x3;
    spi3OutputIfaceDataPtr->outputDeviceExtension.envoyCe2Ce4OutputAttr.outputBaseAddress = tempData;

    return error;
}




/************************************************************************************/
/*||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||*/
/************************************************************************************/

/*--------------------------------------------------------------------------*

   FUNCTION:  ENVOY_SetSpi3PortCtrlReal

   DESCRIPTION: This function actually processess the TXC_IfSPI3_PortCtrlSet
                API function.

   INPUTS:  Same as TXC_IfSPI3_PortCtrlSet except for the interfaceId

   RETURNS:  TXC_NO_ERR or an appropriate specific error code listed in
   appendix.

   CAVEATS: None

   REVISION HISTORY:

    Rev #     Date          Author                Description
   -----    -------      ------------         ----------------------
   0.5.0    6/03/04      F. Giannella         Initial release (beta)
 *--------------------------------------------------------------------------*/

TXC_U16BIT ENVOY_SetSpi3PortCtrlReal (TXC_U16BIT handle, TXC_U16BIT port, 
                                        TXC_IfSPI3_PORT_CTRL_STRUCT  *spi3PortCtrlPtr)
{
    TXC_U16BIT error = TXC_NO_ERR;
    TXC_U16BIT deviceType;
    TXC_BATCH_REG_ACCESS_32BIT_STRUCT batchData;
    TXC_REG_ACCESS_32BIT_STRUCT regData[2];
    TXC_REG_32 * baseAddr;
    TXC_SEM_ID semId;
    TXC_U16BIT rtosError;
    ENVOY_ISPI_CFG_STRUCT *spi3InputCtrlPtr;
    ENVOY_OSPI_CFG_STRUCT *spi3OutputCtrlPtr;

    /* First, fill the batch platform header. This function requires 2
       registers to be written */
    memset (&regData[0], 0, (2 * sizeof(TXC_REG_ACCESS_32BIT_STRUCT) ) );
    batchData.regDataPtr = &regData[0];
    batchData.writeVerifyFlag = TXC_WRITE_VERIFY_FLAG;
    batchData.semId = TXC_NULL;
    batchData.regCount = 2;

    /* First, get the device type. */
    deviceType = ENVOY_DbGetDeviceType (handle);
    if ((deviceType != ENVOY_CE2) && (deviceType != ENVOY_CE4) )
    {
       return TXC_DEVICE_NOT_FOUND_ERR;
    }

    if (port == ENVOY_SPI3_ALL_PORTS)
    {
        if (deviceType == ENVOY_CE2)
        {
            regData[0].mask = 0xFFFF;  /* reg0: input; reg1: output */
            regData[1].mask = 0xFFFF;
        }
        else  /* that is, deviceType == ENVOY_CE4 */ 
        {
            regData[0].mask = 0xFFFFFFFF; /* reg0: input; reg1: output */
            regData[1].mask = 0xFFFFFFFF;
        }
    }
    else
    {
        regData[0].mask = 1 << port; /* reg0: input; reg1: output */
        regData[1].mask = 1 << port;
    }

    /* determine the base address of the device */
    baseAddr = (TXC_REG_32 *) ENVOY_DbGetDeviceAddr (handle);

    spi3InputCtrlPtr = (ENVOY_ISPI_CFG_STRUCT *) (baseAddr + ENVOY_ISPI_CFG_OFFSET);
    regData[0].addr = (TXC_REG_32 *) &spi3InputCtrlPtr->iSpi3PortEnableReg;

    spi3OutputCtrlPtr = (ENVOY_OSPI_CFG_STRUCT *) (baseAddr + ENVOY_OSPI_CFG_OFFSET);
    regData[1].addr = (TXC_REG_32 *) &spi3OutputCtrlPtr->oSpi3PortEnableReg;


    /* Set Port Status */
    switch (spi3PortCtrlPtr->spi3PortEnableMode)
    {
        case TXC_IfSPI3_NO_DIR_ENABLED:
            regData[0].data = 0;
            regData[1].data = 0;
            break;

        case TXC_IfSPI3_BOTH_DIR_ENABLED:
            regData[0].data = regData[0].mask;
            regData[1].data = regData[1].mask;
            break;

        case TXC_IfSPI3_INPUT_ENABLED_ONLY:
            regData[0].data = regData[0].mask;
            regData[1].data = 0;
            break;

        case TXC_IfSPI3_OUTPUT_ENABLED_ONLY:
            regData[0].data = 0;
            regData[1].data = regData[1].mask;
            break;

        default:
            return error = TXC_GEN_ERR;  /* added so that lint will be happy */
            break;                       /* however, it should never get here */
    }

    /* Semaphore protect the writing of the device POS phy config and the
       writing of the L3 emulation block registers. */
    semId = ENVOY_DbGetSemId();
    rtosError = TXC_SemWait (semId, TXC_OS_SEM_WAIT_FOREVER);
    if (rtosError != TXC_NO_ERR)
    {
        return TXC_OS_RESOURCE_ERR;
    }
    error = TXC_BatchReg32BitWrite (&batchData);
    /* release the semaphore */
    rtosError = TXC_SemPost (semId);
    if (rtosError != TXC_NO_ERR)
    {
        return TXC_OS_RESOURCE_ERR;
    }
    return error;
}




/************************************************************************************/
/*||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||*/
/************************************************************************************

   FUNCTION:  ENVOY_GetSpi3PortCtrlReal

   DESCRIPTION: This function actually processess the TXC_IfSPI3_PortCtrlGet
                API function.

   INPUTS:  Same as TXC_IfSPI3_PortCtrlGet, except for the interfaceId

   RETURNS:  TXC_NO_ERR or an appropriate specific error code listed in appendix.

   CAVEATS:  None.

   REVISION HISTORY:

    Rev #     Date          Author                Description
   -----    -------      ------------         ----------------------
   0.5.0    6/03/04      F. Giannella         Initial release (beta)
 *--------------------------------------------------------------------------*/

TXC_U16BIT ENVOY_GetSpi3PortCtrlReal (TXC_U16BIT handle, TXC_U16BIT port,
                                        TXC_IfSPI3_PORT_CTRL_STRUCT  *spi3PortCtrlPtr)
{
    TXC_U16BIT error = TXC_NO_ERR;
    TXC_BATCH_REG_ACCESS_32BIT_STRUCT batchData;
    TXC_REG_ACCESS_32BIT_STRUCT regData[4];
    TXC_REG_32            *baseAddr;
    ENVOY_ISPI_CFG_STRUCT *spi3InputCtrlPtr;
    ENVOY_OSPI_CFG_STRUCT *spi3OutputCtrlPtr;

    /* First, fill the batch platform header. This function requires 5
       registers to be read */
    memset (&regData[0], 0, (2 * sizeof(TXC_REG_ACCESS_32BIT_STRUCT) ) );
    batchData.regDataPtr = &regData[0];
    batchData.writeVerifyFlag = TXC_WRITE_VERIFY_FLAG;
    batchData.semId = ENVOY_DbGetSemId();
    batchData.regCount = 2;

    /* determine the base address of the device */
    baseAddr = (TXC_REG_32 *) ENVOY_DbGetDeviceAddr (handle);

    /* Setup the addresses and masks to read for SPI-3 interface */
    spi3InputCtrlPtr = (ENVOY_ISPI_CFG_STRUCT *) (baseAddr + ENVOY_ISPI_CFG_OFFSET);
    regData[0].addr = (TXC_REG_32 *) &spi3InputCtrlPtr->iSpi3PortEnableReg;

    spi3OutputCtrlPtr = (ENVOY_OSPI_CFG_STRUCT *) (baseAddr + ENVOY_OSPI_CFG_OFFSET);
    regData[1].addr = (TXC_REG_32 *) &spi3OutputCtrlPtr->oSpi3PortEnableReg;

    /* reg0: input; reg1: output */

    regData[0].mask = 1 << port; 
    regData[1].mask = 1 << port;

    /* Read the registers and return the data */

    error = TXC_BatchReg32BitRead (&batchData);

    if (error == TXC_NO_ERR)
    {
         if ((regData[0].data == 0 ) && (regData[1].data == 0))
         {
             spi3PortCtrlPtr->spi3PortEnableMode = TXC_IfSPI3_NO_DIR_ENABLED;
         }
         else if ((regData[0].data != 0 ) && (regData[1].data != 0))
         {
             spi3PortCtrlPtr->spi3PortEnableMode = TXC_IfSPI3_BOTH_DIR_ENABLED;
         }
         else if ((regData[0].data != 0 ) && (regData[1].data == 0))
         {
             spi3PortCtrlPtr->spi3PortEnableMode = TXC_IfSPI3_INPUT_ENABLED_ONLY;
         }
         else
         {
             spi3PortCtrlPtr->spi3PortEnableMode = TXC_IfSPI3_OUTPUT_ENABLED_ONLY;
         }
    }
    return error;
}