txc_envoy_spi3_real.c

TranSwitch Envoy CE2 & Envoy CE4 设备驱动及编程指南

    regData[1].addr = (TXC_REG_32 *) &spi3CfgPtr->iSpi3StpaPoliceEnableReg;

    regData[0].mask = (ISPI_REG_2000_MASK | ISPI_PARITY_MODE_MASK) | ISPI_AGGR_BYTE_POS_MASK;
    regData[1].mask = ISPI_REG_2018_MASK;

    /* Read the registers and return the data */    
    error = TXC_BatchReg32BitRead (&batchData);
    if (error == TXC_NO_ERR)
    {
        error = TXC_ENVOY_DeviceExPinRtrv (handle, &pinData);
        if (error != TXC_NO_ERR)
        {
            return error;
        }
        else
        {
            tempData = (regData[0].data >> 16 ) & 0x1;
            if ((tempData == 0x1) && (pinData.spi3InputMode == ENVOY_DEV_PIN_SPI3_PHY_MODE))
            {
                spi3InputIfaceDataPtr->inputMode = TXC_IfSPI3_PHY_LAYER_SINGLE_PHY;
            }
            else if ((tempData == 0x0) && (pinData.spi3InputMode == ENVOY_DEV_PIN_SPI3_PHY_MODE))
            {
                spi3InputIfaceDataPtr->inputMode = TXC_IfSPI3_PHY_LAYER_MULTI_PHY;
            }
            else if ((tempData == 0x1) && (pinData.spi3InputMode == ENVOY_DEV_PIN_SPI3_LINK_MODE))
            {
                spi3InputIfaceDataPtr->inputMode = TXC_IfSPI3_LINK_LAYER_SINGLE_PHY;
            }
            else
            {
                spi3InputIfaceDataPtr->inputMode = TXC_IfSPI3_LINK_LAYER_MULTI_PHY;
            }
        }
    }
    /* return pi-configurable parameter */
    switch (pinData.spi3WidthMode)
    {
        case ENVOY_DEV_PIN_SPI3_32_BITS:
            spi3InputIfaceDataPtr->inputBusWidth = TXC_IfSPI3_BUS_WIDTH_32BIT;
            break;

        case ENVOY_DEV_PIN_SPI3_16_BITS:
            spi3InputIfaceDataPtr->inputBusWidth = TXC_IfSPI3_BUS_WIDTH_16BIT;
            break;

        case ENVOY_DEV_PIN_SPI3_8_BITS:
            spi3InputIfaceDataPtr->inputBusWidth = TXC_IfSPI3_BUS_WIDTH_8BIT;
            break;

        default:
            spi3InputIfaceDataPtr->inputBusWidth = TXC_IfSPI3_BUS_WIDTH_NONE;
            break;
    }

    tempData = (regData[0].data >> 20) & 0x3;
    if (tempData & 0x2)  /* that is, if parity checking is enabled */
    {
        if (tempData == 0x2)
        {
            spi3InputIfaceDataPtr->inputParityCheckingMode = TXC_IfSPI3_EVEN_PARITY;
        }
        else
        {
            spi3InputIfaceDataPtr->inputParityCheckingMode = TXC_IfSPI3_ODD_PARITY;
        }
    }
    else
    {
        spi3InputIfaceDataPtr->inputParityCheckingMode = TXC_IfSPI3_NO_PARITY;
    }

    tempData = (regData[0].data >> 17) & 0x7;
    if (!tempData & 0x1)
    {
        spi3InputIfaceDataPtr->inputDeviceExtension.envoyCe2Ce4InputAttr.inputAggregationMode = TXC_IfSPI3_INPUT_AGGR_DISABLED;
    }
    else
    {
        switch (tempData >> 1)
        {
            case 0:
                spi3InputIfaceDataPtr->inputDeviceExtension.envoyCe2Ce4InputAttr.inputAggregationMode = TXC_IfSPI3_INPUT_AGGR_PORT_POS_BYTE0;
                break;

            case 1:
                spi3InputIfaceDataPtr->inputDeviceExtension.envoyCe2Ce4InputAttr.inputAggregationMode = TXC_IfSPI3_INPUT_AGGR_PORT_POS_BYTE1;
                break;

            case 2:
                spi3InputIfaceDataPtr->inputDeviceExtension.envoyCe2Ce4InputAttr.inputAggregationMode = TXC_IfSPI3_INPUT_AGGR_PORT_POS_BYTE2;
                break;

            case 3:
                spi3InputIfaceDataPtr->inputDeviceExtension.envoyCe2Ce4InputAttr.inputAggregationMode = TXC_IfSPI3_INPUT_AGGR_PORT_POS_BYTE3;
                break;

            default:
                break;  /* should never happen */
        }
    }

    tempData = (regData[1].data) & 0x1;
    if (tempData)
    {
        spi3InputIfaceDataPtr->inputDeviceExtension.envoyCe2Ce4InputAttr.inputStpaViolationDiscardEnable = TXC_TRUE;
    }
    else
    {
        spi3InputIfaceDataPtr->inputDeviceExtension.envoyCe2Ce4InputAttr.inputStpaViolationDiscardEnable = TXC_FALSE;
    }

    return error;
}




/************************************************************************************/
/*||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||*/
/************************************************************************************/

/*--------------------------------------------------------------------------*

   FUNCTION:  ENVOY_SetSpi3OutputIfaceReal

   DESCRIPTION: This function actually processess the TXC_IfSPI3_OutputIfaceSet
                API function.

   INPUTS:  Same as TXC_IfSPI3_OutputIfaceSet

   RETURNS:  TXC_NO_ERR or an appropriate specific error code listed in
   appendix.

   CAVEATS: None

   REVISION HISTORY:

    Rev #     Date          Author                Description
   -----    -------      ------------         ----------------------
   0.5.0    6/03/04      F. Giannella         Initial release (beta)
 *--------------------------------------------------------------------------*/

TXC_U16BIT ENVOY_SetSpi3OutputIfaceReal (TXC_U16BIT handle,
                                         TXC_IfSPI3_OUTPUT_STRUCT *spi3OutputIfaceDataPtr)
{
    TXC_U16BIT error = TXC_NO_ERR;
    TXC_BATCH_REG_ACCESS_32BIT_STRUCT batchData;
    TXC_REG_ACCESS_32BIT_STRUCT regData[4];
    TXC_REG_32 * baseAddr;
    TXC_REG_32 tmpReg0, tmpReg1, tmpReg2;
    TXC_SEM_ID semId;
    TXC_U16BIT rtosError;
    ENVOY_OSPI_CFG_STRUCT * spi3CfgPtr;
    ENVOY_DEV_EXT_PIN_STRUCT pinData;

    /* fill the structure with 0 */
    memset ((void *) &pinData, 0, sizeof (pinData));

    /* First, fill the batch platform header. This function requires 2
       registers to be written */
    memset (&regData[0], 0, (3 * sizeof(TXC_REG_ACCESS_32BIT_STRUCT) ) );
    batchData.regDataPtr = &regData[0];
    batchData.writeVerifyFlag = TXC_WRITE_VERIFY_FLAG;
    batchData.semId = TXC_NULL;
    batchData.regCount = 3;

    /* reg0 = 2200, bit 16: input mode (multi, single or link mode*/
    regData[0].mask = OSPI_REG_2200_MASK;
    regData[1].mask = OSPI_REG_2210_MASK;
    regData[2].mask = OSPI_REG_2214_MASK;

    /* Set mode */
    switch (spi3OutputIfaceDataPtr->outputMode)
    {
        case TXC_IfSPI3_PHY_LAYER_SINGLE_PHY:
            tmpReg0 = OSPI_SPHY_ENB;
            break;

        case TXC_IfSPI3_PHY_LAYER_MULTI_PHY:
            tmpReg0 = 0;
            break;

        case TXC_IfSPI3_LINK_LAYER_SINGLE_PHY:
            tmpReg0 = OSPI_SPHY_ENB;
            break;

        case TXC_IfSPI3_LINK_LAYER_MULTI_PHY:

            tmpReg0 = 0;
            break;

        default:
            return error = TXC_GEN_ERR;  /* added so that lint will be happy */
            break;                       /* however, it should never get here */
    }

    /* Set Input Parit Check Mode */
    if (spi3OutputIfaceDataPtr->outputParityGenerationMode == TXC_IfSPI3_ODD_PARITY)
    {
        regData[0].mask |= OSPI_PARITY_MODE_MASK;
        tmpReg0 |= (OSPI_PARITY_ENB | OSPI_ODD_PARITY_ENB);
    }
    if (spi3OutputIfaceDataPtr->outputParityGenerationMode == TXC_IfSPI3_EVEN_PARITY)
    {
        regData[0].mask |= OSPI_PARITY_MODE_MASK;
        tmpReg0 |= OSPI_PARITY_ENB;
    }
    /* Note if(spi3OutputIfaceDataPtr->outputParityGenerationMode == TXC_IfSPI3_NO_PARITY) 
            "0" will be written into enable parity bit 8 and bit 7 will be untouched */


    /* Set Pause Timer Mode */
    if (spi3OutputIfaceDataPtr->outputPauseTimerMode == TXC_IfSPI3_OUTPUT_PAUSE_2_CYCLE)
    {
        tmpReg0 |= OSPI_2_CYCLE_ENB;
    }

    /* Set Aggregation Mode */
    if (spi3OutputIfaceDataPtr->outputDeviceExtension.envoyCe2Ce4OutputAttr.outputAggregationEnable == TXC_TRUE)
    {
        tmpReg0 |= OSPI_AGGREGATION_ENB;
    }


     /* Configure the Base Adress (offset */
     tmpReg0 |= (spi3OutputIfaceDataPtr->outputDeviceExtension.envoyCe2Ce4OutputAttr.outputBaseAddress) & 0x3;


    /* Set Output Flow Control Mode */
    switch (spi3OutputIfaceDataPtr->outputFlowControlMode)
    {
        case TXC_IfSPI3_OUTPUT_FLOW_CONTROL_NONE:
            tmpReg1 = 0;
            tmpReg2 = 0;
            break;

        case TXC_IfSPI3_OUTPUT_FLOW_CONTROL_STPA:

            tmpReg1 = OSPI_STPA_ENB;
            tmpReg2 = 0;
            break;

        case TXC_IfSPI3_OUTPUT_FLOW_CONTROL_PTPA:
            tmpReg1 = 0;
            tmpReg2 = OSPI_PTPA_ENB;
            break;

        case TXC_IfSPI3_OUTPUT_FLOW_CONTROL_STPA_PTPA:
            tmpReg1 = OSPI_STPA_ENB;
            tmpReg2 = OSPI_PTPA_ENB;
            break;

        default:
            return error = TXC_GEN_ERR;  /* added so that lint will be happy */
            break;
    }


    /* determine the base address of the device */
    baseAddr = (TXC_REG_32 *) ENVOY_DbGetDeviceAddr (handle);
    spi3CfgPtr = (ENVOY_OSPI_CFG_STRUCT *) (baseAddr + ENVOY_OSPI_CFG_OFFSET);
    regData[0].data = tmpReg0;
    regData[1].data = tmpReg1;
    regData[2].data = tmpReg2;

    regData[0].addr = (TXC_REG_32 *) &spi3CfgPtr->oSpi3CfgReg;
    regData[1].addr = (TXC_REG_32 *) &spi3CfgPtr->oSpi3StpaEnableReg;
    regData[2].addr = (TXC_REG_32 *) &spi3CfgPtr->oSpi3PtpaEnableReg;

       
    /* Semaphore protect the writing of the device POS phy config and the
       writing of the L3 emulation block registers. */
    semId = ENVOY_DbGetSemId();
    rtosError = TXC_SemWait (semId, TXC_OS_SEM_WAIT_FOREVER);
    if (rtosError != TXC_NO_ERR)
    {
        return TXC_OS_RESOURCE_ERR;
    }
    error = TXC_BatchReg32BitWrite (&batchData);
    /* release the semaphore */
    rtosError = TXC_SemPost (semId);
    if (rtosError != TXC_NO_ERR)
    {
        return TXC_OS_RESOURCE_ERR;
    }
    return error;
}




/************************************************************************************/
/*||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||*/
/************************************************************************************

   FUNCTION:  ENVOY_GetSpi3OutputIfaceReal

   DESCRIPTION: This function actually processess the TXC_IfSPI3_OutputIfaceGet
                API function.

   INPUTS:  Same as TXC_IfSPI3_OutputIfaceGet, except for the interfaceId

   RETURNS:  TXC_NO_ERR or an appropriate specific error code listed in appendix.

   CAVEATS:  None.

   REVISION HISTORY:

    Rev #     Date          Author                Description
   -----    -------      ------------         ----------------------
   0.5.0    6/03/04      F. Giannella         Initial release (beta)
 *--------------------------------------------------------------------------*/

TXC_U16BIT ENVOY_GetSpi3OutputIfaceReal (TXC_U16BIT handle, 
                                         TXC_IfSPI3_OUTPUT_STRUCT *spi3OutputIfaceDataPtr)
{
    TXC_U16BIT error = TXC_NO_ERR;
    TXC_BATCH_REG_ACCESS_32BIT_STRUCT batchData;
    TXC_REG_ACCESS_32BIT_STRUCT regData[4];
    TXC_REG_32            *baseAddr, tempData, ptpaStpa;
    ENVOY_OSPI_CFG_STRUCT * spi3CfgPtr;
    ENVOY_DEV_EXT_PIN_STRUCT pinData;

    /* fill the structure with 0 */
    memset ((void *) &pinData, 0, sizeof (pinData));

    /* First, fill the batch platform header. This function requires 5
       registers to be read */
    memset (&regData[0], 0, (3 * sizeof(TXC_REG_ACCESS_32BIT_STRUCT) ) );
    batchData.regDataPtr = &regData[0];
    batchData.writeVerifyFlag = TXC_WRITE_VERIFY_FLAG;
    batchData.semId = ENVOY_DbGetSemId();
    batchData.regCount = 3;

    /* determine the base address of the device */
    baseAddr = (TXC_REG_32 *) ENVOY_DbGetDeviceAddr (handle);
    spi3CfgPtr = (ENVOY_OSPI_CFG_STRUCT *) (baseAddr + ENVOY_OSPI_CFG_OFFSET);

    /* Setup the addresses and masks to read for SPI-3 interface */
    regData[0].addr = (TXC_REG_32 *) &spi3CfgPtr->oSpi3CfgReg;
    regData[1].addr = (TXC_REG_32 *) &spi3CfgPtr->oSpi3StpaEnableReg;
    regData[2].addr = (TXC_REG_32 *) &spi3CfgPtr->oSpi3PtpaEnableReg;