txc_envoy_spi3_support.h

TranSwitch Envoy CE2 & Envoy CE4 设备驱动及编程指南

/*--------------------------------------------------------------------------

  *******                           ****
     *     *****     **    *    *  *       *    *   *  *****   ****   *    *
     *     *    *   *  *   **   *  *       *    *   *    *    *    *  *    *
     *     *    *  *    *  * *  *   ****   *    *   *    *    *       ******
     *     *****   ******  *  * *       *  * ** *   *    *    *       *    *
     *     *   *   *    *  *   **  *    *  **  **   *    *    *    *  *    *
     *     *    *  *    *  *    *   ****   *    *   *    *     ****   *    *

                        Proprietary and Confidential 

    This program is made available only to customers and prospective customers 
of TranSwitch Corporation under license and may be used only with TranSwitch 
semi-conductor products.

                      Copyright(c) 2004 TranSwitch Inc.

 --------------------------------------------------------------------------

             *******  **      **  **        **   ********   **      **
             *******  ***     **  **        **  **********  **      **
             **       ** *    **  **        **  **      **   **    **
             *****    **  *   **   **      **   **      **     *  *
             *****    **   *  **    **    **    **      **      **
             **       **    * **     **  **     **      **      **
             *******  **     ***      ****      **********      **
             *******  **      **       **        ********       **

 --------------------------------------------------------------------------
                           TranSwitch Envoy-CE2/CE4
                                Device Driver
 --------------------------------------------------------------------------

  Workfile:     txc_envoy_spi3_support.h

  Description:  This header file contains support function for the POS-SPI-3
                interface support functions.

 --------------------------------------------------------------------------
                              Revision History
 --------------------------------------------------------------------------
    Rev #     Date          Author                Description
   -----    -------      ------------         ----------------------
   0.5.0    6/03/04      F. Giannella         Initial release (beta)
 *--------------------------------------------------------------------------*/



#ifndef TXC_ENVOY_SPI3_SUPPORT_H
#define TXC_ENVOY_SPI3_SUPPORT_H


/****************************************************************************
 **                                Defines                                 **
 ****************************************************************************/
/* ISPI */

#define ISPI_MAX_FLOW_CTRL_THRSLD     0xFF
#define ISPI_MIN_FLOW_CTRL_THRSLD     0x2

#define ISPI_REG_2000_MASK            0x00230000  /* it does not include bits 18,19 and 20 */
#define ISPI_SPHY_ENB                 0x00010000
#define ISPI_PARITY_MODE_MASK         0x00100000  /* bit 20: parity mode mask  */
#define ISPI_ODD_PARITY_ENB           0x00100000  /* bit 20: odd parity enable */
#define ISPI_PARITY_ENB               0x00200000  /* bit 21: parity enable     */
#define ISPI_AGGR_BYTE_POS_MASK       0x000C0000  /* bits 19:18: aggregation byte position */
#define ISPI_AGGR_BYTE0               0x00020000
#define ISPI_AGGR_BYTE1               0x00060000
#define ISPI_AGGR_BYTE2               0x000A0000
#define ISPI_AGGR_BYTE3               0x000E0000

#define ISPI_REG_2018_MASK            0x00000001
#define ISPI_STPA_VIOLATION_ENB       0x00000001


/* OSPI */

#define OSPI_MAX_FLOW_CTRL_THRSLD     0xFF
#define OSPI_MIN_FLOW_CTRL_THRSLD     0x2
#define OSPI_MAX_CHUNK_SIZE           0xFF


#define OSPI_REG_2200_MASK            0x00000177  /* bits 0, 1, 2, 4, 5, 6, 8 (it does not include bit 7) */
#define OSPI_SPHY_ENB                 0x00000020  /* bit 5: single-phy enable    */
#define OSPI_PARITY_MODE_MASK         0x00000080  /* bit 7: parity mode mask     */
#define OSPI_ODD_PARITY_ENB           0x00000080  /* bit 7: odd parity enable    */
#define OSPI_PARITY_ENB               0x00000100  /* bit 8: parity enable        */
#define OSPI_2_CYCLE_ENB              0x00000010  /* bit 4: 2-cycle pause enable */
#define OSPI_AGGREGATION_ENB          0x00000040  /* bit 7: aggregation enable   */

#define OSPI_OUTPUT_MODE_MASK         0x00000200  /* bit 9: output data transfer mask   */
#define OSPI_PACKET_MODE_ENB          0x00000200  /* bit 9: packet data transfer enable */

#define OSPI_REG_2210_MASK            0x00000001
#define OSPI_STPA_ENB                 0x00000001

#define OSPI_REG_2214_MASK            0x00000001
#define OSPI_PTPA_ENB                 0x00000001

/************************************************************************************/
/*||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||*/
/************************************************************************************/



/****************************************************************************
 **                            Data Structures                             **
 ****************************************************************************/



/****************************************************************************
 **                          Function Prototypes                           **
 ****************************************************************************/


/* SPI-3 validation functions */


TXC_U16BIT ENVOY_SetSpi3InputIfaceValid (TXC_U16BIT handle, TXC_U8BIT interfaceId,
           TXC_IfSPI3_INPUT_STRUCT *spi3InputIfaceDataPtr);

TXC_U16BIT ENVOY_GetSpi3InputIfaceValid
           (TXC_U16BIT handle, TXC_U8BIT interfaceId);

TXC_U16BIT ENVOY_SetSpi3OutputIfaceValid (TXC_U16BIT handle, TXC_U8BIT interfaceId,
            TXC_IfSPI3_OUTPUT_STRUCT *spi3OutputIfaceDataPtr);

TXC_U16BIT ENVOY_GetSpi3OutputIfaceValid (TXC_U16BIT handle, TXC_U8BIT interfaceId);

TXC_U16BIT ENVOY_SetSpi3PortCtrlValid (TXC_U16BIT handle, TXC_U8BIT interfaceId,
           TXC_U16BIT port, TXC_IfSPI3_PORT_CTRL_STRUCT  *spi3PortCtrlPtr);

TXC_U16BIT ENVOY_GetSpi3PortCtrlValid (TXC_U16BIT handle, TXC_U8BIT interfaceId, TXC_U16BIT port);

TXC_U16BIT ENVOY_SetSpi3InputFlowCtrlCfgValid (TXC_U16BIT handle, TXC_U8BIT interfaceId,
           TXC_U16BIT port, TXC_IfSPI3_INPUT_FLOW_CTRL_STRUCT  *spi3InputFlowCtrlDataPtr);

TXC_U16BIT ENVOY_GetSpi3InputFlowCtrlCfgValid (TXC_U16BIT handle, TXC_U8BIT interfaceId, TXC_U16BIT port);

TXC_U16BIT ENVOY_SetSpi3OutputFlowCtrlCfgValid (TXC_U16BIT handle, TXC_U8BIT interfaceId,
           TXC_U16BIT port, TXC_IfSPI3_OUTPUT_FLOW_CTRL_STRUCT  *spi3OutputFlowCtrlDataPtr);

TXC_U16BIT ENVOY_GetSpi3OutputFlowCtrlCfgValid (TXC_U16BIT handle, TXC_U8BIT interfaceId, TXC_U16BIT port);

TXC_U16BIT ENVOY_RtrvSpi3ExtGlobalCountersValid (TXC_U16BIT handle, TXC_U8BIT interfaceId);

TXC_U16BIT ENVOY_RtrvSpi3InputGlobalStatusValid (TXC_U16BIT handle, TXC_U8BIT interfaceId);

TXC_U16BIT ENVOY_SetSpi3OutputPortCfgValid (TXC_U16BIT handle, TXC_U8BIT interfaceId, TXC_U16BIT port);

TXC_U16BIT ENVOY_GetSpi3OutputPortCfgValid (TXC_U16BIT handle, TXC_U8BIT interfaceId, TXC_U16BIT port);

TXC_U16BIT ENVOY_RtrvSpi3PortStatisticsValid (TXC_U16BIT handle, TXC_U8BIT interfaceId, TXC_U16BIT port);


/* virtual functions */
#ifdef TXC_ENVOY_VIRTUAL_DEVICE_MODE


#endif /* TXC_ENVOY_VIRTUAL_DEVICE_MODE */

/* Live functions */
#ifndef TXC_ENVOY_VIRTUAL_DEVICE_MODE


TXC_U16BIT ENVOY_SetSpi3InputIfaceReal
    (TXC_U16BIT handle, TXC_IfSPI3_INPUT_STRUCT *spi3InputIfaceDataPtr);

TXC_U16BIT ENVOY_GetSpi3InputIfaceReal
    (TXC_U16BIT handle, TXC_IfSPI3_INPUT_STRUCT *spi3InputIfaceDataPtr);

TXC_U16BIT ENVOY_SetSpi3OutputIfaceReal
    (TXC_U16BIT handle, TXC_IfSPI3_OUTPUT_STRUCT *spi3OutputIfaceDataPtr);

TXC_U16BIT ENVOY_GetSpi3OutputIfaceReal
    (TXC_U16BIT handle, TXC_IfSPI3_OUTPUT_STRUCT *spi3OutputIfaceDataPtr);

TXC_U16BIT ENVOY_SetSpi3PortCtrlReal
    (TXC_U16BIT handle, TXC_U16BIT port, TXC_IfSPI3_PORT_CTRL_STRUCT  *spi3PortCtrlPtr);

TXC_U16BIT ENVOY_GetSpi3PortCtrlReal
    (TXC_U16BIT handle, TXC_U16BIT port, TXC_IfSPI3_PORT_CTRL_STRUCT  *spi3PortCtrlPtr);

TXC_U16BIT ENVOY_SetSpi3InputFlowCtrlCfgReal
    (TXC_U16BIT handle, TXC_U16BIT port, TXC_IfSPI3_INPUT_FLOW_CTRL_STRUCT  *spi3InputFlowCtrlDataPtr);

TXC_U16BIT ENVOY_GetSpi3InputFlowCtrlCfgReal
    (TXC_U16BIT handle, TXC_U16BIT port, TXC_IfSPI3_INPUT_FLOW_CTRL_STRUCT  *spi3InputFlowCtrlDataPtr);

TXC_U16BIT ENVOY_SetSpi3OutputFlowCtrlCfgReal
    (TXC_U16BIT handle, TXC_U16BIT port, TXC_IfSPI3_OUTPUT_FLOW_CTRL_STRUCT  *spi3OutputFlowCtrlDataPtr);

TXC_U16BIT ENVOY_GetSpi3OutputFlowCtrlCfgReal
    (TXC_U16BIT handle, TXC_U16BIT port, TXC_IfSPI3_OUTPUT_FLOW_CTRL_STRUCT  *spi3OutputFlowCtrlDataPtr);

TXC_U16BIT ENVOY_RtrvSpi3ExtGlobalCountersReal
    (TXC_U16BIT handle, TXC_IfSPI3_EXT_GLBL_CTR_STRUCT *spi3ExtGlobalCountersDataPtr);

TXC_U16BIT ENVOY_RtrvSpi3InputGlobalStatusReal
    (TXC_U16BIT handle, TXC_IfSPI3_EXT_INPUT_GLBL_STATUS_STRUCT *spi3InputGlobalStatusDataPtr);

TXC_U16BIT ENVOY_SetSpi3OutputPortCfgReal
    (TXC_U16BIT handle, TXC_U16BIT port, TXC_IfSPI3_EXT_OUTPUT_PORT_CFG_STRUCT  *spi3OutputPortCfgDataPtr);

TXC_U16BIT ENVOY_GetSpi3OutputPortCfgReal (TXC_U16BIT handle,TXC_U16BIT port,
                        TXC_IfSPI3_EXT_OUTPUT_PORT_CFG_STRUCT  *spi3OutputPortCfgDataPtr);

TXC_U16BIT ENVOY_RtrvSpi3PortStatisticsReal (TXC_U16BIT handle, TXC_U16BIT port,
                         TXC_IfSPI3_PORT_STATISTICS_STRUCT *spi3PortStatisticsDataPtr);



#endif /* NOT TXC_ENVOY_VIRTUAL_DEVICE_MODE */


	
 /****************************************************************************
 **                              End of Module                             **
 ****************************************************************************/

#endif /* TXC_ENVOY_SPI3_SUPPORT_H */