default.rul

MicroWind第2代

MICROWIND 2.0a
*
* Rule File for HCMOS7, ST Microelectronics
* Date : 17 Jun 97 by Etienne Sicard
*        24 Jun 97 Add text
*        04 May 98 Fit with hcmos7 data file
*        14 May 98 Fit with MOS measurements ST
*	 27 May 98 Fabrice r205 modification
*	 29 may 98 Etienne CIF modification for HCMOS7 layers
*        21 Jun 98 Size of diffs
*        03 Nov 98 Thickness of diffs & wells
*        11 Nov 98 Height of metallizations
*        05 Jan 99 rise time
*        27 Apr 99 fit model with measures
*        16 May 99 via/contact r603
*
* Check : CIF layer nbr
* label nbr
*
* status : preliminary
*
NAME ST 0.25祄 - 6 Metal
*
lambda = 0.125     (Lambda is set to half the gate size)
metalLayers = 6    (Number of metal layers : 6)
lowK = 3.9         (inter-metal oxide)  
*
* Design rules associated to each layer
*
* Well (Gds2 level 1)
r101 = 10    (well width)
r102 = 11    (well spacing)
*
* Diffusion (N+ 16, P+ 17, active 2)
*
r201 = 4     (diffusion width)
r202 = 4     (diffusion spacing)
r203 = 6     (border of nwell on diffp)
r204 = 6     (nwell to next diffn)
r205 = 4     (polarisation to diff)
*
* Poly (13)
*
r301 = 2     (poly width)
r302 = 2     (ngate width)
r303 = 2     (pgate width)
r304 = 3     (poly spacing)
r305 = 2     (spacing poly and unrelated diff)
r306 = 4     (width of drain and source diff)
r307 = 3     (extra gate poly)
* Contact (19)
r401 = 2     (contact width)
r402 = 5     (contact spacing)
r404 = 2     (metal,poly,diff border for contact)
*  metal (23)
r501 = 4    (metal width)
r502 = 4    (metal spacing)
*  via  (25)
r601 = 2    (Via width)
r602 = 5    (Spacing)
r603 = 0    (via/contact)
r604 = 2    (border of metal&metal2)
*  metal 2 (27)
r701 = 4    (Metal 2 width)
r702 = 4    (spacing)
*  via 2 (32)
r801 = 2    (Via width)
r802 = 5    (Spacing)
r804 = 2    (border of metal2&metal3)
*  metal 3 (34)
r901 = 4    (width)
r902 = 4    (spacing)
*  via 3 (35)
ra01 = 2    (Via width)
ra02 = 5    (Spacing)
ra04 = 2    (border of metal3&metal4)
*  metal 4 (36)
rb01 = 4    (width)
rb02 = 4    (spacing)
*  via 4 (52)
rc01 = 2    (Via width)
rc02 = 5    (Spacing)
rc04 = 3    (border of metal4&metal5)
*  metal 5 (53)
rd01 = 8    (width)
rd02 = 8    (spacing)
*  via 5 (54)
re01 = 4    (Via width)
re02 = 6    (Spacing)
re04 = 2    (border of metal5&metal6)
*  metal 6 (55)
rf01 = 8    (width)
rf02 = 15   (spacing)
*
* Passivation nitride (31) and pad rules
*
rp01 = 800  (Pad width)
rp02 = 800  (Pad spacing)
rp03 = 40   (Border of Vias)
rp04 = 40   (Border of metals)
rp05 = 200  (to unrelated active areas)
*
* Thickness of conductors for process aspect
* All in 祄
*
heepi = 4
thepi = 1
thpoly = 0.30
hepoly = 0.25
thdn = 0.5
thdp = 0.5
thnw = 1.5
thme = 0.5
heme = 0.9
thm2 = 0.5
hem2 = 2.2
thm3 = 0.5
hem3 = 3.3
thm4 = 0.5
hem4 = 4.4
thm5 = 0.7
hem5 = 5.5
thm6 = 0.7
hem6 = 7.0
thpass = 0.5
hepass = 8.0
thnit = 0.6
henit = 8.5
*
* Resistances
* Unit is ohm/square
*
repo = 4
reco = 2
reme = 0.250
revi = 2
rem2 = 0.055
rev2 = 3
rem3 = 0.055
rev3 = 3
rem4 = 0.055
rev4 = 2
rem5 = 0.035
rev5 = 1
rem6 = 0.035
*
*
* Parasitic capacitances
*
cpoOxyde= 4600 (Surface capacitance Poly/Thin oxyde aF/祄2)
cpobody = 80    (Poly/Body)
cmebody = 28
cmelineic = 42
cmepoly = 60
cm2body = 13
cm2lineic = 36
cm2metal = 38
cm3body = 8
cm3lineic = 33
cm4body = 6
cm4lineic = 30
cm5body = 5
cm5lineic = 31
cm6body = 4
cm6lineic = 30
cgsn = 500          ( Gate/source capa of nMOS)
cgsp = 500
*
* Vertical crosstalk
*
cm2me = 50
cm3m2 = 50
cm4m3 = 50
cm5m4 = 50
cm6m5 = 50
*
* Lateral Crosstalk
*
cmextk = 10    (Lineic capacitance for crosstalk coupling in aF/祄)
cm2xtk = 10    (C is computed using Cx=cmextk*l/spacing)
cm3xtk = 10
cm4xtk = 10
cm5xtk = 10
cm6xtk = 10
*
* Junction capacitances
*
cdnpwell = 350  (n+/psub)
cdpnwell = 300  (p+/nwell)
cnwell = 250    (nwell/psub)
cpwell = 100    (pwell/nsub)
cldn = 120      (Lineic capacitance N+/P- aF/祄)
cldp = 120      (Idem for P+/N-)
*
* Nmos Model 3 parameters
*
NMOS
l3vto = 0.5
l3vmax = 130e3
l3gamma = 0.4
l3theta = 0.3
l3kappa = 0.01
l3phi = 0.7
l3ld = 0.05
l3kp = 300e-6
l3nss = 0.07
*
* Pmos Model 3
*
PMOS
l3vto = -0.5
l3vmax = 100e3
l3gamma = 0.4
l3theta = 0.3
l3kappa = 0.01
l3phi = 0.7
l3ld = 0.05
l3kp = 120e-6
l3nss = 0.07
*
* MM9 Model parameters
*
* Nmos MM9
*
NMOS
vtor = 0.60
slvto = 0.01e-6
swvto = 0.0e-6
lap = 0.021e-6
wot = 0.033e-6
kor = 0.25
slko = 0.0
swko = 0.0
ler = 10e-6
wer = 10e-6
phib = 0.65
betsq = 220e-6
zet1 = 0.35
mor = 0.368
gamo = 0.010
slgamo = 0e-6
gam1 = 0.034
slgam1 = -0.5e-6
swgam1 = 0.05e-6
the1 = 0.12
slthe1 = 0.10e-6
swthe1 = 0.00e-6
the2 = 0.13
slthe2 = -0.02e-6
swthe2 = 0.06e-6
the3 = 0.06
slthe3 = 0.06e-6
swthe3 = -0.08e-6
vsbtr = 0.156
vsbxr = 2.0
*
* Pmos MM9
*
PMOS
vtor = 0.60
slvto = 0.0
swvto = 0.0
lap = 0.017e-6
wot = 4.5e-8
kor = 0.25
slko = 0.0
swko = 0.0
ler = 10e-6
wer = 10e-6
betsq = 80e-6
zet1 = 1.43
mor = 0.33
phib = 0.65
gamo = 0.010
slgamo = 2.6e-15
gam1 = 0.045
slgam1 = -0.1e-6
swgam1 = 0.0
the1 = 0.44
slthe1 = 0.072e-6
swthe1 = -5e-8
the2 = 0.25
slthe2 = -3.67e-8
swthe2 = 3.0e-8
the3 = 0.002
slthe3 = 0.43e-8
swthe3 = 2.0e-8
vsbtr = 0.156
vsbxr = 0.073
*
* CIF & Gds2 Layers
* MicroWind layer, CIF layer, Gds2 layer, overetch
*
cif nwell 1 1 0.0
cif diffp 17 17 0.25
cif diffn 16 16 0.25
cif aarea 2 2 0
cif poly 13 13 0.0
cif contact 19 19 0.025
cif metal 23 23 0
cif via 25 25 0.075
cif metal2 27 27 0
cif via2 32 32 0.075
cif metal3 34 34 0
cif via3 35 35 0.075
cif metal4 36 36 0
cif via4 52 52 0.075
cif metal5 53 53 0.0
cif via5 54 54 0.05
cif metal6 55 55 0.0
cif passiv 31 31 0.0
cif text 60 60 0.0
*
*
* MicroWind simulation parameters
*
deltaT = 1.5e-12   (Minimum simulation interval dT)
vdd = 2.5
temperature = 27
riseTime = 0.05
*
* End ST HCMOS7 0.25 祄
*
*