dreg.sym

来自「dsch第2版本」· SYM 代码 · 共 28 行

SYM  #dreg
BB(0,0,30,25)
TITLE 12 8  #dreg
MODEL 860
DATE 13.10.1999
REC(-25,-10,0,0)
VIS 5
PIN(0,5,0.000,0)D
PIN(0,15,0.000,0)RST
PIN(15,25,0.000,0)H
PIN(30,15,4.0,1)Q
PIN(30,5,4.0,1)nQ
LIG(0,15,5,15)
LIG(0,5,5,5)
LIG(15,25,15,20)
LIG(25,15,30,15)
LIG(25,5,30,5)
LIG(25,20,5,20)
LIG(25,0,25,20)
LIG(5,0,25,0)
LIG(5,20,5,0)
LIG(14,20,15,18)
LIG(15,18,16,20)
VLG    module dreg(D,RST,H,Q,nQ);
VLG     input D,RST,H;
VLG     output Q,nQ;
VLG    endmodule
FSYM