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DSCH 2.0c
VERSION 03/11/99 15:44:38
BB(-70,-140,150,35)
SYM #Y
BB(-70,-50,-20,-10)
TITLE -70 -16 #kbd
MODEL 85
PROP
REC(-70,-50,40,40,r)
VIS 3
PIN(-20,-15,0.000,0.000)Y1
PIN(-20,-25,0.000,0.000)Y2
PIN(-20,-35,0.000,0.000)Y3
PIN(-20,-45,0.000,0.000)Y4
LIG(-70,-10,-30,-10)
LIG(-70,-50,-70,-10)
LIG(-70,-50,-30,-50)
LIG(-30,-50,-30,-10)
LIG(-70,-30,-30,-30)
LIG(-50,-50,-50,-10)
LIG(-60,-10,-60,-50)
LIG(-70,-40,-30,-40)
LIG(-40,-50,-40,-10)
LIG(-70,-20,-30,-20)
LIG(-30,-15,-20,-15)
LIG(-20,-25,-30,-25)
LIG(-30,-35,-20,-35)
LIG(-20,-45,-30,-45)
LIG(-66,-12,-66,-18)
LIG(-66,-18,-64,-18)
LIG(-64,-18,-64,-12)
LIG(-64,-12,-66,-12)
LIG(-54,-12,-54,-18)
LIG(-46,-18,-44,-18)
LIG(-44,-18,-44,-16)
LIG(-44,-16,-46,-16)
LIG(-46,-16,-46,-12)
LIG(-46,-12,-44,-12)
LIG(-36,-12,-34,-12)
LIG(-34,-18,-36,-18)
LIG(-34,-18,-34,-12)
LIG(-36,-16,-34,-16)
LIG(-66,-28,-66,-24)
LIG(-66,-24,-64,-24)
LIG(-64,-28,-64,-22)
LIG(-54,-28,-56,-28)
LIG(-56,-28,-56,-26)
LIG(-56,-26,-54,-26)
LIG(-54,-26,-54,-22)
LIG(-54,-22,-56,-22)
LIG(-46,-28,-46,-22)
LIG(-46,-22,-44,-22)
LIG(-44,-22,-44,-26)
LIG(-44,-26,-46,-26)
LIG(-36,-28,-34,-28)
LIG(-34,-28,-34,-22)
LIG(-66,-32,-66,-38)
LIG(-66,-38,-64,-38)
LIG(-64,-38,-64,-32)
LIG(-64,-32,-66,-32)
LIG(-66,-36,-64,-36)
LIG(-56,-38,-56,-34)
LIG(-56,-34,-54,-34)
LIG(-56,-38,-54,-38)
LIG(-54,-38,-54,-32)
LIG(-46,-38,-44,-38)
LIG(-44,-38,-44,-32)
LIG(-44,-32,-46,-32)
LIG(-46,-32,-46,-36)
LIG(-46,-36,-44,-36)
LIG(-36,-38,-36,-32)
LIG(-36,-32,-34,-32)
LIG(-34,-32,-34,-34)
LIG(-34,-34,-36,-34)
LIG(-64,-46,-66,-46)
LIG(-66,-46,-66,-42)
LIG(-66,-42,-64,-42)
LIG(-56,-44,-56,-42)
LIG(-56,-42,-54,-42)
LIG(-54,-42,-54,-48)
LIG(-56,-44,-54,-44)
LIG(-44,-42,-46,-42)
LIG(-46,-42,-46,-48)
LIG(-46,-48,-44,-48)
LIG(-46,-46,-44,-46)
LIG(-36,-42,-36,-48)
LIG(-36,-48,-34,-48)
LIG(-36,-44,-34,-44)
FSYM
SYM #vss
BB(140,-133,150,-125)
TITLE 144 -128 #vss
MODEL 0
PROP
REC(140,-135,0,0,b)
VIS 0
PIN(145,-135,0.000,0.000)vss
LIG(145,-135,145,-130)
LIG(140,-130,150,-130)
LIG(140,-127,142,-130)
LIG(142,-127,144,-130)
LIG(144,-127,146,-130)
LIG(146,-127,148,-130)
FSYM
SYM #button1
BB(-24,21,-15,29)
TITLE -20 25 #button
MODEL 59
PROP
REC(-23,22,6,6,r)
VIS 1
PIN(-15,25,0.000,0.000)InitialCarry
LIG(-16,25,-15,25)
LIG(-24,29,-24,21)
LIG(-16,29,-24,29)
LIG(-16,21,-16,29)
LIG(-24,21,-16,21)
LIG(-23,28,-23,22)
LIG(-17,28,-23,28)
LIG(-17,22,-17,28)
LIG(-23,22,-17,22)
FSYM
SYM #fadd
BB(25,-5,65,35)
TITLE 35 5 #fadd
MODEL 6000
PROP
REC(35,-5,20,40,r)
VIS 5
PIN(25,25,0.000,0.000)C
PIN(25,15,0.000,0.000)B
PIN(25,5,0.000,0.000)A
PIN(65,15,1.000,0.000)Sum
PIN(65,5,1.000,0.000)Carry
LIG(25,25,35,25)
LIG(25,15,35,15)
LIG(25,5,35,5)
LIG(55,15,65,15)
LIG(55,5,65,5)
LIG(35,-5,35,35)
LIG(35,-5,55,-5)
LIG(55,-5,55,35)
LIG(55,35,35,35)
VLG module fadd( C,B,A,Sum,Carry);
VLG input C,B,A;
VLG output Sum,Carry;
VLG wire w1,w2,w3,w4;
VLG xor xor21(Sum,w1,C);
VLG xor xor22(w1,A,B);
VLG nand nand21(w4,B,A);
VLG nand nand22(w3,B,C);
VLG nand nand23(w2,A,C);
VLG nand nand31(Carry,w4,w3,w2);
VLG endmodule
FSYM
SYM #fadd
BB(25,-140,65,-100)
TITLE 35 -130 #fadd
MODEL 6000
PROP
REC(35,-140,20,40,r)
VIS 5
PIN(25,-110,0.000,0.000)C
PIN(25,-120,0.000,0.000)B
PIN(25,-130,0.000,0.000)A
PIN(65,-120,1.000,0.000)Sum
PIN(65,-130,1.000,0.000)Carry
LIG(25,-110,35,-110)
LIG(25,-120,35,-120)
LIG(25,-130,35,-130)
LIG(55,-120,65,-120)
LIG(55,-130,65,-130)
LIG(35,-140,35,-100)
LIG(35,-140,55,-140)
LIG(55,-140,55,-100)
LIG(55,-100,35,-100)
VLG module fadd( C,B,A,Sum,Carry);
VLG input C,B,A;
VLG output Sum,Carry;
VLG wire w1,w2,w3,w4;
VLG xor xor21(Sum,w1,C);
VLG xor xor22(w1,A,B);
VLG nand nand21(w4,B,A);
VLG nand nand22(w3,B,C);
VLG nand nand23(w2,A,C);
VLG nand nand31(Carry,w4,w3,w2);
VLG endmodule
FSYM
SYM #fadd
BB(25,-95,65,-55)
TITLE 35 -85 #fadd
MODEL 6000
PROP
REC(35,-95,20,40,r)
VIS 5
PIN(25,-65,0.000,0.000)C
PIN(25,-75,0.000,0.000)B
PIN(25,-85,0.000,0.000)A
PIN(65,-75,1.000,0.000)Sum
PIN(65,-85,1.000,0.000)Carry
LIG(25,-65,35,-65)
LIG(25,-75,35,-75)
LIG(25,-85,35,-85)
LIG(55,-75,65,-75)
LIG(55,-85,65,-85)
LIG(35,-95,35,-55)
LIG(35,-95,55,-95)
LIG(55,-95,55,-55)
LIG(55,-55,35,-55)
VLG module fadd( C,B,A,Sum,Carry);
VLG input C,B,A;
VLG output Sum,Carry;
VLG wire w1,w2,w3,w4;
VLG xor xor21(Sum,w1,C);
VLG xor xor22(w1,A,B);
VLG nand nand21(w4,B,A);
VLG nand nand22(w3,B,C);
VLG nand nand23(w2,A,C);
VLG nand nand31(Carry,w4,w3,w2);
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