mux2kbd.sch
来自「dsch第2版本」· SCH 代码 · 共 531 行 · 第 1/2 页
SCH
531 行
VLG // transmission gate description
VLG // 28.08.97
VLG module tgate(in,en,out);
VLG input in,en;
VLG output out;
VLG wire nEn;
VLG not cell1(nEn,en);
VLG nmos dev1(out,in,en);
VLG pmos dev2(out,in,nEn);
VLG endmodule
FSYM
SYM #mynot
BB(50,140,85,160)
TITLE 65 150 #mynot
MODEL 101
PROP
REC(40,120,0,0,r)
VIS 5
PIN(50,150,0.000,0.000)in
PIN(85,150,0.050,0.000)out
LIG(75,148,79,150)
LIG(50,150,60,150)
LIG(60,160,60,140)
LIG(60,140,75,140)
LIG(75,140,75,160)
LIG(75,160,60,160)
LIG(75,150,85,150)
VLG not mynot(out,in);
FSYM
SYM #tgate
BB(70,30,90,50)
TITLE 85 35 #tgate
MODEL 6000
PROP 2.4 1.2
REC(0,-5,0,0,r)
VIS 5
PIN(70,45,0.000,0.000)in
PIN(80,35,0.000,0.000)en
PIN(90,45,0.050,0.100)out
LIG(70,45,75,45)
LIG(80,35,80,45)
LIG(85,45,90,45)
LIG(75,40,75,50)
LIG(85,40,85,50)
LIG(75,40,85,50)
LIG(75,50,85,40)
VLG // Etienne Sicard
VLG // transmission gate description
VLG // 28.08.97
VLG module tgate(in,en,out);
VLG input in,en;
VLG output out;
VLG wire nEn;
VLG not cell1(nEn,en);
VLG nmos dev1(out,in,en);
VLG pmos dev2(out,in,nEn);
VLG endmodule
FSYM
SYM #tgate
BB(70,40,90,60)
TITLE 85 45 #tgate
MODEL 6000
PROP 2.4 1.2
REC(0,-5,0,0,r)
VIS 5
PIN(70,55,0.000,0.000)in
PIN(80,45,0.000,0.000)en
PIN(90,55,0.050,0.100)out
LIG(70,55,75,55)
LIG(80,45,80,55)
LIG(85,55,90,55)
LIG(75,50,75,60)
LIG(85,50,85,60)
LIG(75,50,85,60)
LIG(75,60,85,50)
VLG // Etienne Sicard
VLG // transmission gate description
VLG // 28.08.97
VLG module tgate(in,en,out);
VLG input in,en;
VLG output out;
VLG wire nEn;
VLG not cell1(nEn,en);
VLG nmos dev1(out,in,en);
VLG pmos dev2(out,in,nEn);
VLG endmodule
FSYM
SYM #tgate
BB(70,50,90,70)
TITLE 85 55 #tgate
MODEL 6000
PROP 2.4 1.2
REC(0,0,0,0,r)
VIS 5
PIN(70,65,0.000,0.000)in
PIN(80,55,0.000,0.000)en
PIN(90,65,0.050,0.100)out
LIG(70,65,75,65)
LIG(80,55,80,65)
LIG(85,65,90,65)
LIG(75,60,75,70)
LIG(85,60,85,70)
LIG(75,60,85,70)
LIG(75,70,85,60)
VLG // Etienne Sicard
VLG // transmission gate description
VLG // 28.08.97
VLG module tgate(in,en,out);
VLG input in,en;
VLG output out;
VLG wire nEn;
VLG not cell1(nEn,en);
VLG nmos dev1(out,in,en);
VLG pmos dev2(out,in,nEn);
VLG endmodule
FSYM
SYM #tgate
BB(70,60,90,80)
TITLE 85 65 #tgate
MODEL 6000
PROP 2.4 1.2
REC(0,0,0,0,r)
VIS 5
PIN(70,75,0.000,0.000)in
PIN(80,65,0.000,0.000)en
PIN(90,75,0.050,0.100)out
LIG(70,75,75,75)
LIG(80,65,80,75)
LIG(85,75,90,75)
LIG(75,70,75,80)
LIG(85,70,85,80)
LIG(75,70,85,80)
LIG(75,80,85,70)
VLG // Etienne Sicard
VLG // transmission gate description
VLG // 28.08.97
VLG module tgate(in,en,out);
VLG input in,en;
VLG output out;
VLG wire nEn;
VLG not cell1(nEn,en);
VLG nmos dev1(out,in,en);
VLG pmos dev2(out,in,nEn);
VLG endmodule
FSYM
SYM #tgate
BB(90,95,110,115)
TITLE 105 100 #tgate
MODEL 6000
PROP 2.4 1.2
REC(-5,20,0,0,r)
VIS 5
PIN(90,110,0.000,0.000)in
PIN(100,100,0.000,0.000)en
PIN(110,110,0.050,0.100)out
LIG(90,110,95,110)
LIG(100,100,100,110)
LIG(105,110,110,110)
LIG(95,105,95,115)
LIG(105,105,105,115)
LIG(95,105,105,115)
LIG(95,115,105,105)
VLG // Etienne Sicard
VLG // transmission gate description
VLG // 28.08.97
VLG module tgate(in,en,out);
VLG input in,en;
VLG output out;
VLG wire nEn;
VLG not cell1(nEn,en);
VLG nmos dev1(out,in,en);
VLG pmos dev2(out,in,nEn);
VLG endmodule
FSYM
SYM #tgate
BB(90,85,110,105)
TITLE 105 90 #tgate
MODEL 6000
PROP 2.4 1.2
REC(0,0,0,0,r)
VIS 5
PIN(90,100,0.000,0.000)in
PIN(100,90,0.000,0.000)en
PIN(110,100,0.050,0.100)out
LIG(90,100,95,100)
LIG(100,90,100,100)
LIG(105,100,110,100)
LIG(95,95,95,105)
LIG(105,95,105,105)
LIG(95,95,105,105)
LIG(95,105,105,95)
VLG // Etienne Sicard
VLG // transmission gate description
VLG // 28.08.97
VLG module tgate(in,en,out);
VLG input in,en;
VLG output out;
VLG wire nEn;
VLG not cell1(nEn,en);
VLG nmos dev1(out,in,en);
VLG pmos dev2(out,in,nEn);
VLG endmodule
FSYM
SYM #vss
BB(120,2,130,10)
TITLE 124 7 #vss
MODEL 0
PROP
REC(120,0,0,0,b)
VIS 0
PIN(125,0,0.000,0.000)vss
LIG(125,0,125,5)
LIG(120,5,130,5)
LIG(120,8,122,5)
LIG(122,8,124,5)
LIG(124,8,126,5)
LIG(126,8,128,5)
FSYM
CNC(100 150)
CNC(140 90)
CNC(140 45)
CNC(145 100)
CNC(145 55)
CNC(150 110)
CNC(150 65)
CNC(155 120)
CNC(155 75)
LIG(50,45,70,45)
LIG(50,55,70,55)
LIG(50,65,70,65)
LIG(50,75,70,75)
LIG(110,120,155,120)
LIG(110,55,90,55)
LIG(150,110,110,110)
LIG(145,100,110,100)
LIG(125,0,155,0)
LIG(40,150,50,150)
LIG(50,120,90,120)
LIG(50,110,90,110)
LIG(50,100,90,100)
LIG(50,90,90,90)
LIG(50,150,50,130)
LIG(50,130,80,130)
LIG(80,130,80,35)
LIG(140,90,110,90)
LIG(85,150,100,150)
LIG(110,75,155,75)
LIG(100,150,100,80)
LIG(110,45,140,45)
LIG(140,45,140,40)
LIG(110,45,90,45)
LIG(145,40,145,50)
LIG(145,50,145,55)
LIG(145,55,110,55)
LIG(150,40,150,65)
LIG(110,65,90,65)
LIG(150,65,110,65)
LIG(155,40,155,75)
LIG(110,75,90,75)
LIG(140,45,140,90)
LIG(145,55,145,100)
LIG(150,65,150,110)
LIG(155,75,155,120)
FFIG C:\Dsch 2.0\Manual\Mux2Kbd.sch
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